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      • 參數(shù)資料
        型號: PSD9135V70MT
        廠商: 意法半導體
        英文描述: 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer; Package: TSSOP 8 3.0x3.0x0.95 mm; No of Pins: 8; Container: Rail; Qty per Container: 100
        中文描述: Flash在系統(tǒng)可編程ISP的外設的8位微控制器
        文件頁數(shù): 70/110頁
        文件大小: 1737K
        代理商: PSD9135V70MT
        PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
        70/110
        JTAG Extensions
        TSTAT and TERR are two JTAG extension signals
        enabled by an “ISC_ENABLE” command received
        over the four standard JTAG signals (TMS, TCK,
        TDI, and TDO). They are used to speed Program
        and Erase cycles by indicating status on PSD sig-
        nals instead of having to scan the status out seri-
        ally using the standard JTAG channel. See
        Application Note
        AN1153
        .
        TERR indicates if an error has occurred when
        erasing a sector or programming a byte in Flash
        memory. This signal goes Low (active) when an
        Error condition occurs, and stays Low until an
        “ISC_CLEAR” command is executed or a chip Re-
        set (RESET) pulse is received after an
        “ISC_DISABLE” command.
        TSTAT behaves the same as Ready/Busy de-
        scribed in the section entitled
        Ready/Busy
        (PC3), page 20
        . TSTAT is High when the PSD de-
        vice is in READ Mode (primary and secondary
        Flash memory contents can be read). TSTAT is
        Low when Flash memory Program or Erase cycles
        are in progress, and also when data is being writ-
        ten to the secondary Flash memory.
        TSTAT and TERR can be configured as open-
        drain type signals during an “ISC_ENABLE” com-
        mand. This facilitates a wired-OR connection of
        TSTAT signals from multiple PSD devices and a
        wired-OR connection of TERR signals from those
        same devices. This is useful when several PSD
        devices are “chained” together in a JTAG environ-
        ment.
        Security and Flash memory Protection
        When the security bit is set, the device cannot be
        read on a Device Programmer or through the
        JTAG Port. When using the JTAG Port, only a Full
        Chip Erase command is allowed.
        All other Program, Erase and Verify commands
        are blocked. Full Chip Erase returns the part to a
        non-secured blank state. The Security Bit can be
        set in PSDsoft Express Configuration.
        All primary and secondary Flash memory sectors
        can individually be sector protected against era-
        sures. The sector protect bits can be set in PSD-
        soft Express Configuration.
        Table 34. JTAG Port Signals
        Port C Pin
        JTAG Signals
        Description
        PC0
        TMS
        Mode Select
        PC1
        TCK
        Clock
        PC3
        TSTAT
        Status
        PC4
        TERR
        Error Flag
        PC5
        TDI
        Serial Data In
        PC6
        TDO
        Serial Data Out
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