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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD934512MIT

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器

    

    
文件頁(yè)數(shù)：
62/110頁(yè)

    

    
文件大?。?/td>
1737K

    

    
代理商：
PSD934512MIT


    

    

    

	
    
    
    

    
    
	
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    62/110
    POWER MANAGEMENT
    All PSD devices offer configurable power saving
    options. These options may be used individually or
    in combinations, as follows:
    All memory blocks in a PSD (primary and 
    secondary Flash memory, and SRAM) are 
    built with power management technology. In 
    addition to using special silicon design 
    methodology, power management technology 
    puts the memories into standby mode when 
    address/data inputs are not changing (zero 
    DC current). As soon as a transition occurs on 
    an input, the affected memory “wakes up”, 
    changes and latches its outputs, then goes 
    back to standby. The designer does 
    not
    have 
    to do anything special to achieve memory 
    standby mode when no inputs are changing—
    it happens automatically.
    The PLD sections can also achieve Stand-by 
    mode when its inputs are not changing, as 
    described in the sections on the Power 
    Management Mode Registers (PMMR).
    As with the Power Management mode, the 
    Automatic Power Down (APD) block allows 
    the PSD to reduce to stand-by current 
    automatically. The APD Unit can also block 
    MCU address/data signals from reaching the 
    memories and PLDs. This feature is available 
    on all the devices of the PSD family. The APD 
    Unit is described in more detail in the sections 
    entitled 
    Automatic Power-down (APD) Unit 
    and Power-down Mode, page 63
    .
    Built in logic monitors the Address Strobe of the 
    MCU for activity. If there is no activity for a 
    certain time period (MCU is asleep), the APD 
    Unit initiates Power-down mode (if enabled). 
    Once in Power-down mode, all address/data 
    signals are blocked from reaching PSD memory 
    and PLDs, and the memories are deselected 
    internally. This allows the memory and PLDs to 
    ■
    ■
    remain in standby mode even if the address/
    data signals are changing state externally 
    (noise, other devices on the MCU bus, etc.). 
    Keep in mind that any unblocked PLD input 
    signals that are changing states keeps the PLD 
    out of Stand-by mode, but not the memories.
    PSD Chip Select Input (CSI, PD2) can be 
    used to disable the internal memories, placing 
    them in standby mode even if inputs are 
    changing. This feature does not block any 
    internal signals or disable the PLDs. This is a 
    good alternative to using the APD Unit. There 
    is a slight penalty in memory access time 
    when PSD Chip Select Input (CSI, PD2) 
    makes its initial transition from deselected to 
    selected.
    The PMMRs can be written by the MCU at run-
    time to manage power. All PSD supports 
    “blocking bits” in these registers that are set to 
    block designated signals from reaching both 
    PLDs. Current consumption of the PLDs is 
    directly related to the composite frequency of 
    the changes on their inputs (see Figure 
    35
     and 
    Figure 36., page 72
    ). Significant power 
    savings can be achieved by blocking signals 
    that are not used in DPLD or CPLD logic 
    equations.
    PSD devices have a Turbo Bit in PMMR0. This 
    bit can be set to turn the Turbo mode off (the 
    default is with Turbo mode turned on). While 
    Turbo mode is off, the PLDs can achieve 
    standby current when no PLD inputs are 
    changing (zero DC current). Even when inputs 
    do change, significant power can be saved at 
    lower frequencies (AC current), compared to 
    when Turbo mode is on. When the Turbo mode 
    is on, there is a significant DC current 
    component and the AC component is higher.
    ■
    ■
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD934512MT
Low Power Economy BiCMOS Current Mode PWM 8-PDIP -40 to 85

    

    
PSD934515JIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD934515JT
Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85

    

    
PSD934515MIT
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

    

    
PSD934515MT
Low Power Economy BiCMOS Current Mode PWM 8-TSSOP -40 to 85

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD934F2-15J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 2M 150ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD934F290J
 制造商:WSI 功能描述:

    

    
PSD934F2-90J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PLCC-52 5V 2M 90NS

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD934F2-90M
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 2M 90ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD934F2V-15J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.3V 2M 150ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
    
    
    
	
    	
    
    
     
     
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