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    參數(shù)資料
    型號: PSD935F2V-A-15M
    廠商: 意法半導體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲系統(tǒng)
    文件頁數(shù): 79/91頁
    文件大?。?/td> 488K
    代理商: PSD935F2V-A-15M
    PSD9XX Family
    PSD935G2
    78
    Microcontroller Interface – PSD935G2AC/DC Parameters
    (3.0 V to 3.6 V Versions)
    Symbol
    Parameter
    Min
    Typ
    Max
    Unit
    Flash Program
    8.5
    sec
    Flash Bulk Erase (Preprogrammed to 00) (Note 1)
    3
    30
    sec
    Flash Bulk Erase
    10
    sec
    t
    WHQV3
    t
    WHQV2
    t
    WHQV1
    Sector Erase (Preprogrammed to 00)
    1
    30
    sec
    Sector Erase
    2.2
    sec
    Word Program
    14
    1200
    μs
    Program/Erase Cycles (Per Sector)
    100,000
    cycles
    t
    WHWLO
    Sector Erase Time-Out
    100
    μs
    t
    Q7VQV
    DQ7 Valid to Output Valid (Data Polling)
    (Note 2)
    30
    ns
    Flash Program, Write and Erase Times
    (3.0 V to 3.6 V Versions)
    -90
    -12
    Symbol
    Parameter
    Conditions
    Min
    Max
    Min
    Max
    Unit
    t
    ISCCF
    t
    ISCCH
    t
    ISCCL
    t
    ISCCF-P
    t
    ISCCH-P
    t
    ISCCL-P
    t
    ISCPSU
    t
    ISCPH
    t
    ISCPCO
    t
    ISCPZV
    t
    ISCPVZ
    TCK Clock Frequency (except for PLD)
    TCK Clock High Time
    TCK Clock Low Time
    TCK Clock Frequency (for PLD only)
    TCK Clock High Time (for PLD only)
    TCK Clock Low Time (for PLD only)
    ISC Port Set Up Time
    ISC Port Hold Up Time
    ISC Port Clock to Output
    ISC Port High-Impedance to Valid Output
    ISC Port Valid Output to High-Impedance
    (Note 1)
    (Note 1)
    (Note 1)
    (Note 2)
    (Note 2)
    (Note 2)
    15
    12
    MHz
    ns
    ns
    MHz
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    30
    30
    40
    40
    2
    2
    240
    240
    11
    5
    240
    240
    12
    5
    26
    26
    26
    32
    32
    32
    ISC Timing
    (3.0 V to 3.6 V Versions)
    NOTES:
    1. Programmed to all zeros before erase.
    2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading.
    NOTES:
    1. For “non-PLD” programming, erase or in ISC by-pass mode.
    2. For program or erase PLD only.
    相關(guān)PDF資料
    PDF描述
    PSD935F2V-A-15MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935F2V-A-15U Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935F2V-A-15UI Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 27pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080&quot; x 0.050&quot; x 0.055&quot;; Container: Bag; Features: MIL-PRF-55681: P Failure Rate
    PSD935F2V-A-20B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935F2V-A-20B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
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