參數(shù)資料
型號: PSD935F3V-15B81
廠商: 意法半導體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù): 32/91頁
文件大?。?/td> 488K
代理商: PSD935F3V-15B81
PSD935G2
PSD9XX Family
31
The
PSD935G2
Functional
Blocks
(cont.)
9.1.5 Memory ID Registers
The 8-bit read only memory status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0
and Memory ID1 registers. The content of the registers are defined as follow:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Memory_ID0 Register
Main Flash Size
(Bit)
none
256K
512K
1M
2M
4M
8M
F_size3
0
0
0
0
0
0
0
F_size2
0
0
0
0
1
1
1
F_size1
0
0
1
1
0
0
1
F_size0
0
1
0
1
0
1
0
Bit Definition
SRAM Size
(Bit)
none
16K
32K
64K
S_size3
0
0
0
0
S_size2
0
0
0
0
S_size1
0
0
1
1
S_size0
0
1
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
Memory_ID1 Register
*
Not used bit should be set to zero.
Boot Block Size
(Bit)
none
128K
256K
512K
B_size3
0
0
0
0
B_size2
0
0
0
0
B_size1
0
0
1
1
B_size0
0
1
0
1
Bit Definition
B_type1
0
0
B_type0
0
1
Boot Block Type
Flash
EEPROM
相關PDF資料
PDF描述
PSD935F3V-15B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F3V-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關代理商/技術參數(shù)
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