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      參數(shù)資料
      型號： PSD935G1V-A-12J
      廠商： 意法半導(dǎo)體
      英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
      中文描述： 在8片位微控制器可配置存儲系統(tǒng)
      文件頁數(shù)： 62/91頁
      文件大?。?/td> 488K
      代理商： PSD935G1V-A-12J
      9.5.3.4 Reset of Flash Erase and Programming Cycles
      An external reset on the RESET pin will also reset the internal Flash memory state
      machine. When the Flash is in programming or erase mode, the RESET pin will terminate
      the programming or erase operation and return the Flash back to read mode in tNLNH-A
      (minimum 25 μs) time.
      9.6 Programming In-Circuit using the JTAG-ISP Interface
      The JTAG-ISP interface on the PSD935G2 can be enabled on Port E (see Table 29). All
      memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
      programmed through the JTAG-ISC interface. A blank part can be mounted on a printed
      circuit board and programmed using JTAG-ISP.
      The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
      signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
      erase operations.
      PSD935G2
      PSD9XX Family
      61
      Port E Pin
      PE0
      PE1
      PE2
      PE3
      PE4
      PE5
      JTAG Signals
      TMS
      TCK
      TDI
      TDO
      TSTAT
      TERR
      Description
      Mode Select
      Clock
      Serial Data In
      Serial Data Out
      Status
      Error Flag
      Table 29. JTAG Port Signals
      The
      PSD935G2
      Functional
      Blocks
      (cont.)
      *
      SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
      Port Configuration
      MCU I/O
      PLD Output
      Power On Reset
      Input Mode
      Valid after internal
      PSD configuration
      bits are loaded
      Tri-stated
      Tri-stated
      Warm Reset
      Input Mode
      Valid
      Power Down Mode
      Unchanged
      Depend on inputs to
      PLD (address are
      blocked in PD mode)
      Not defined
      Tri-stated
      Address Out
      Data Port
      Tri-stated
      Tri-stated
      Table 28. Status During Power On Reset, Warm Reset and Power Down Mode
      Register
      PMMR0, 2
      VM Register*
      Power On Reset
      Cleared to
      “
      0
      ”
      Initialized based on
      the selection in
      PSDsoft
      Configuration Menu.
      Cleared to
      “
      0
      ”
      Warm Reset
      Unchanged
      Initialized based on
      the selection in
      PSDsoft
      Configuration Menu.
      Cleared to
      “
      0
      ”
      Power Down Mode
      Unchanged
      Unchanged
      All other registers
      Unchanged
      By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E
      are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
      See ST Application Note AN1153 for more details on JTAG In-System-Programming.
      相關(guān)PDF資料
      PDF描述
      PSD935G1V-B-12U Configurable Memory System on a Chip for 8-Bit Microcontrollers
      PSD935G1V-B-12UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
      PSD935G1V-B-15B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
      PSD935G1V-B-15B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
      PSD935G1V-B-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
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