參數(shù)資料
型號： PSD935G1V-A-70B81I
廠商： 意法半導(dǎo)體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù)： 29/91頁
文件大小： 488K
代理商： PSD935G1V-A-70B81I
PSD9XX Family
PSD935G2
28
The
PSD935G2
Functional
Blocks
(cont.)
Level 1
SRAM, I/O
Level 2
Secondary Flash Memory
Highest Priority
Lowest Priority
Level 3
Main Flash Memory
Figure 6. Priority Level of Memory and I/OComponents
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 80C51 and compatible family of microcontrollers, can be configured to have separate
address spaces for code memory (selected using PSEN) and data memory (selected using
RD). Any of the memories within the PSD935G2 can reside in either space or both spaces.
This is controlled through manipulation of the VM register that resides in the PSD
’
s CSIOP
space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and main Flash in Data Space at boot, and
secondary Flash memory in Program Space at boot, and later swap main and secondary
Flash memory. This is easily done with the VM register by using PSDsoft to configure it for
boot up and having the microcontroller change it when desired.
Table 11 describes the VM Register.
Bit 7
PIO_EN
Bit 6* Bit 5*
Bit 4
FL_Data Boot_Data
Bit 3
Bit 2
FL_Code
Bit 1
Bit 0
Boot_Code SRAM_Code
0 = disable
PIO mode
*
*
0 = RD
can
’
t
access
Flash
0 = RD
can
’
t
access
Boot Flash
0 = PSEN
can
’
t
access
Flash
0 = PSEN
can
’
t
access
Boot Flash
0 = PSEN
can
’
t
access
SRAM
1= enable
PIO mode
*
*
1 = RD
access
Flash
1 = RD
access
Boot Flash
1 = PSEN
access
Flash
1 = PSEN
access
Boot Flash
1 = PSEN
access
SRAM
Table 11. VM Register
NOTE:
Bits 6-5 are not used.
相關(guān)PDF資料
PDF描述
PSD935G1V-A-70J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935G1V-A-70JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935G1V-A-70M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935G1V-A-70MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935G1V-A-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD935G2-90U 功能描述:SPLD - 簡單可編程邏輯器件 TQFP-80 5V 4M 90N RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD935G2V-90U 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD835G2V-90U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2-90J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2-90M 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2V-90J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*