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    參數(shù)資料
    型號(hào): PSD954270MIT
    廠商: 意法半導(dǎo)體
    英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
    中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
    文件頁數(shù): 79/110頁
    文件大?。?/td> 1737K
    代理商: PSD954270MIT
    79/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    Table 46. DC Characteristics (3V devices)
    Note: 1. Reset (RESET) has hysteresis. V
    IL1
    is valid at or below 0.2V
    CC
    –0.1. V
    IH1
    is valid at or above 0.8V
    CC
    .
    2. CSI deselected or internal PD is active.
    3. PLD is in non-Turbo mode, and none of the inputs are switching.
    4. Please see
    Figure 36., page 72
    for the PLD current calculation.
    5. I
    OUT
    = 0mA
    Symbol
    Parameter
    Conditions
    Min.
    Typ.
    Max.
    Unit
    V
    IH
    High Level Input Voltage
    3.0 V < V
    CC
    < 3.6 V
    0.7V
    CC
    V
    CC
    +0.5
    V
    V
    IL
    Low Level Input Voltage
    3.0 V < V
    CC
    < 3.6 V
    –0.5
    0.8
    V
    V
    IH1
    Reset High Level Input Voltage
    (Note
    1
    )
    0.8V
    CC
    V
    CC
    +0.5
    V
    V
    IL1
    Reset Low Level Input Voltage
    (Note
    1
    )
    –0.5
    0.2V
    CC
    –0.1
    V
    V
    HYS
    Reset Pin Hysteresis
    0.3
    V
    V
    LKO
    V
    CC
    (min) for Flash Erase and
    Program
    1.5
    2.2
    V
    V
    OL
    Output Low Voltage
    I
    OL
    = 20μA, V
    CC
    = 3.0 V
    0.01
    0.1
    V
    I
    OL
    = 4mA, V
    CC
    = 3.0 V
    0.15
    0.45
    V
    V
    OH
    Output High Voltage Except
    V
    STBY
    On
    I
    OH
    = –20μA, V
    CC
    = 3.0 V
    2.9
    2.99
    V
    I
    OH
    = –1mA, V
    CC
    = 3.0 V
    2.7
    2.8
    V
    V
    OH1
    Output High Voltage V
    STBY
    On
    I
    OH1
    = 1μA
    V
    STBY
    – 0.8
    V
    V
    STBY
    SRAM Stand-by Voltage
    2.0
    V
    CC
    V
    I
    STBY
    SRAM Stand-by Current
    V
    CC
    = 0 V
    0.5
    1
    μA
    I
    IDLE
    Idle Current (V
    STBY
    input)
    V
    CC
    > V
    STBY
    –0.1
    0.1
    μA
    V
    DF
    SRAM Data Retention Voltage
    Only on V
    STBY
    2
    V
    I
    SB
    Stand-by Supply Current
    for Power-down Mode
    CSI >V
    CC
    –0.3 V (Notes
    2,3
    )
    25
    100
    μA
    I
    LI
    Input Leakage Current
    V
    SS
    < V
    IN
    < V
    CC
    –1
    ±0.1
    1
    μA
    I
    LO
    Output Leakage Current
    0.45 < V
    IN
    < V
    CC
    –10
    ±5
    10
    μA
    I
    CC
    (DC)
    (Note
    5
    )
    Operating
    Supply
    Current
    PLD Only
    PLD_TURBO = Off,
    f = 0 MHz (Note
    3
    )
    0
    μA/PT
    PLD_TURBO = On,
    f = 0 MHz
    200
    400
    μA/PT
    Flash memory
    During Flash memory
    WRITE/Erase Only
    10
    25
    mA
    Read only, f = 0 MHz
    0
    0
    mA
    SRAM
    f = 0 MHz
    0
    0
    mA
    I
    CC
    (AC)
    (Note
    5
    )
    PLD AC Adder
    note
    4
    Flash memory AC Adder
    1.5
    2.0
    mA/
    MHz
    SRAM AC Adder
    0.8
    1.5
    mA/
    MHz
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