參數(shù)資料
型號： PSD954315JT
廠商： 意法半導體
元件分類： 基準電壓源/電流源
英文描述： Single Output LDO, 3.0A, Fixed(5.0V), Reverse Current Protection, Thermal Shutdown 3-TO-220 -40 to 85
中文描述： Flash在系統(tǒng)可編程ISP的外設的8位微控制器
文件頁數(shù)： 47/110頁
文件大?。?/td> 1737K
代理商： PSD954315JT
47/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
80C251
The Intel 80C251 MCU features a user-config-
urable bus interface with four possible bus config-
urations, as shown in
Table 18., page 48
.
The first configuration is 80C31-compatible, and
the bus interface to the PSD is identical to that
shown in
Figure 21., page 46
. The second and
third configurations have the same bus connection
as shown in Figure
22
. There is only one Read
Strobe (PSEN) connected to CNTL1 on the PSD.
The A16 connection to PA0 allows for a larger ad-
dress input to the PSD. The fourth configuration is
shown in
Figure 23., page 48
. Read Strobe (RD) is
connected to CNTL1 and Program Select Enable
(PSEN) is connected to CNTL2.
The 80C251 has two major operating modes:
Page mode and Non-page mode. In Non-page
mode, the data is multiplexed with the lower ad-
dress byte, and Address Strobe (ALE/AS, PD0) is
active in every bus cycle. In Page mode, data (D7-
D0) is multiplexed with address (A15-A8). In a bus
cycle where there is a Page hit, Address Strobe
(ALE/AS, PD0) is not active and only addresses
(A7-A0) are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is iden-
tical to Non-Page Mode except the address hold
time and setup time with respect to Address
Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0)
valid to data in valid.
Figure 22. Interfacing the PSD with the 80C251, with One READ Input
Note: 1. The A16 and A17 connections are optional.
2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
27
28
29
30
31
43
42
41
40
39
38
37
36
24
25
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD14
AD15
AD13
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD15
ALE
RD
WR
A16
AD14
14
15
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
X2
X1
RST
EA
A161
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.0
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB
PSD
RESET
RESET
35
16
17
10
RESET
AI02881C
A171
相關(guān)PDF資料
PDF描述
PSD954315MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954315MT Single Output LDO, 3.0A, Fixed(5.0V), Reverse Current Protection, Thermal Shutdown 3-DDPAK/TO-263 -40 to 85
PSD954320JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954320JT Single Output LDO, 3.0A, Adj.(1.22 to 8.5V), Reverse Current Protection, Thermal Shutdown 5-TO-220 -40 to 85
PSD954320MIT Single Output LDO, 3.0A, Adj.(1.22 to 8.5V), Reverse Current Protection, Thermal Shutdown 5-TO-220 -40 to 85
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參數(shù)描述
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