參數(shù)資料
型號: PSD954412JT
廠商: 意法半導(dǎo)體
英文描述: Single Output LDO, 500mA, Fixed(5V), Low Quiescent Current, wide Input Voltage Range 8-SOIC -40 to 85
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 32/110頁
文件大?。?/td> 1737K
代理商: PSD954412JT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
32/110
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
Select (FS0-FS7,
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note
AN1154
.
Figure
12
shows the Page Register. The eight flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
Figure 12. Page Register
RESET
D0- D7
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI02871B
相關(guān)PDF資料
PDF描述
PSD954412MIT Single Output LDO, 500mA, Adj.(15 to 1.25V), Low Quiescent Current, wide Input Voltage Range 8-SOIC -40 to 85
PSD954412MT Single Output LDO, 500mA, Adj.(15 to 1.25V), Low Quiescent Current, wide Input Voltage Range 8-SOIC -40 to 85
PSD954415JIT Single Output LDO, 500mA, Adj.(15 to 1.25V), Low Quiescent Current, wide Input Voltage Range 8-SOIC -40 to 85
PSD954415JT Single Output LDO, 500mA, Adj.(15 to 1.25V), Low Quiescent Current, wide Input Voltage Range 8-SOIC -40 to 85
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