參數(shù)資料
型號： PSD954F2-70J
廠商： 意法半導體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設的8位微控制器
文件頁數(shù)： 15/94頁
文件大小： 476K
代理商： PSD954F2-70J
Preliminary Information
PSD9XX Family
Pin Name
Pin*
(PLCC)
Type
Description
CNTL2
49
I
This pin can be used to input the PSEN (Program Select
Enable) signal from any MCU that uses this signal for code
exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This
port is connected to the PLDs.
Reset
48
I
Active low reset input. Resets I/O Ports and some of the
configuration registers. Must be active at power up.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. General Purpose PLD outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
5. Address inputs. For example, PA0-3 could be used for
A[0:3] when using an 80C51XA in burst mode.
6. As the data bus inputs D[0:7] for non-multiplexed
address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
Note:
PA0-3 can only output CMOS signals with an option
for high slew rate. However, PA4-7 can be configured as
CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
I/O
These pins make up Port B. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. General Purpose PLD outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
Note:
PB0-3 can only output CMOS signals with an option
for high slew rate. However, PB4-7 can be configured as
CMOS or Open Drain Outputs.
52
51
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. TMS Input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. TCK Input for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
11
相關PDF資料
PDF描述
PSD954F2-70M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSLD0J337M GT 4C 4#12 PIN RECP LINE
PSLD1A227M PS/L Series Neocapacitor CONDUCTIVE POLYMER TANTALUM CAPACITORS
相關代理商/技術參數(shù)
參數(shù)描述
PSD954F2-90J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2-90M 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2V-90J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2V-90M 功能描述:SPLD - 簡單可編程邏輯器件 PQFP-52 3V 2M 90NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PS-DA0104-01 制造商:POWER-SYSTEMS 制造商全稱:Power Systems GmbH+Co.KG 功能描述:DC-AC INVERTER UNIT 4 W SINGLE OUTPUTS
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*