參數(shù)資料
型號(hào): PT7C4311WEX
廠商: Pericom
文件頁(yè)數(shù): 16/17頁(yè)
文件大?。?/td> 0K
描述: IC RTC LEAP YEAR Y2K 8SOIC
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 時(shí)鐘/日歷
特點(diǎn): 閏年,方波輸出,Y2K
存儲(chǔ)容量: 56B
時(shí)間格式: HH:MM:SS(24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 1.2 V ~ 5.5 V
電壓 - 電源,電池: 2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): PT7C4311WEXDKR
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PT0322(08/09)
Ver: 2
8
Data Sheet
PT7C4311
Real-time Clock Module (I
2C Bus)
Communication
1.
I
2C Bus Interface
a)
Overview of I
2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
b)
System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
Master
MCU
Slave
RTC
O ther Peripheral
Device
Vcc
SD A
SCL
N ote: W hen there is only one m aster, the M CU is ready for driving SCL to "H " and R
P of S C L m ay not required.
R
P
R
P
Fig.1 System configuration
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