
PRODUCTPREVIEW
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
Table 46. VDD2_REG
Address Offset
0x24
Physical Address
Instance
Description
VDD1 control register
Type
RW
7
6
5
4
3
2
1
0
VGAIN_SEL
ILMAX
TSTEP
ST
Bits
Field Name
Description
Type
Reset
7:6
VGAIN_SEL
Select output voltage multiplication factor: G (EEPROM bits):
RW
0x0
when 00: x1
when 01: TBD
when 10: x2
when 11: x3
5:4
ILMAX
Select maximum load current:
RW
0
when 0: 1.0 A
when 1: > 1.5 A
3:2
TSTEP
Time step: when changing the output voltage, the new value is reached
RW
0x1
through successive 12.5 mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/s (sampling 3 Mhz)
TSTEP[2:0] = 010: 9.4 mV/s (sampling 3 Mhz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/s (sampling 3 Mhz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/s(sampling 3 Mhz/2)
TSTEP[2:0] = 101: 4.7 mV/s(sampling 3 Mhz/3)
TSTEP[2:0] = 110: 3.12 mV/s(sampling 3 Mhz/4)
TSTEP[2:0] = 111: 2.5 mV/s(sampling 3 Mhz/5)
1:0
ST
Supply state (EEPROM bits):
RW
0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On, high power mode
ST[1:0] = 10 : Off
ST[1:0] = 11 : On, low power mode
Table 47. VDD2_OP_REG
Address Offset
0x25
Physical Address
Instance
Description
VDD2 voltage selection register.
This register can be accessed by both control and smartreflex I2C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type
RW
7
6
5
4
3
2
1
0
CMD
SEL
Copyright 2010, Texas Instruments Incorporated
65