V
(1V/div)
TRK
V 2(1V/div)
O
t-Time=20ms/div
V 1(1V/div)
O
V
(1V/div)
TRK
V 2(1V/div)
O
t-Time=400 s/div
m
V 1(1V/div)
O
Prebias Startup Capability
SLTS260E – OCTOBER 2005 – REVISED NOVEMBER 2008 .......................................................................................................................................... www.ti.com
Figure 24. Simultaneous Power Up With Auto-Track
Figure 25. Simultaneous Power Down With Auto-Track
Control
A prebias startup condition occurs as a result of an external voltage being present at the output of a power
module prior to its output becoming active. This often occurs in complex digital systems when current from
another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another
path might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. A
prebias can cause problems with power modules that incorporate synchronous rectifiers. This is because under
most operating conditions, such modules can sink as well as source output current. PTH modules all incorporate
synchronous rectifiers. Those that incorporate the prebias feature do not sink current during startup, or whenever
the Inhibit pin is held low. Start up includes an initial delay (approximately 8–15 ms), followed by the rise of the
output voltage under the control of the module’s internal soft-start mechanism; see
Figure 26.Conditions for PreBias Holdoff
For the module to allow an output prebias voltage to exist (and not sink current), certain conditions must be
maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenever the output is
allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of the ground
signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track disabled (see
Figure 26). To further ensure that the regulator doesn’t sink output current, (even with a ground signal applied to
its Inhibit), the input voltage must always be greater than the applied prebias source. This condition must exist
throughout the power-up sequence.
The soft-start period is complete when the output begins rising above the prebias voltage. Once it is complete
the module functions as normal, and sinks current if a voltage higher than the nominal regulation value is applied
to its output.
Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risen
to either the set-point voltage, or the voltage applied at the module’s Track control pin, whichever is lowest.
Demonstration Circuit
Figure 27 shows the startup waveforms for the demonstration circuit shown in Figure 28. The initial rise in VO2 is the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the
output current from the PTH12010L module (IO2) is negligible until its output voltage rises above the applied
pre-bias.
26
Copyright 2005–2008, Texas Instruments Incorporated