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參數(shù)資料
| 型號： | PW-82520R3-840 |
| 英文描述： | Industrial Control IC |
| 中文描述： | 工業(yè)控制IC |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 191K |
| 代理商： | PW-82520R3-840 |
11
Data Device Corporation
www.ddc-web.com
PW-82520/21N
A-11/01-1000
COMPENSATION
The PI regulator in the PW-82520/21N can be tuned to a specif-
ic load for optimum performance. FIGURE 8 shows the standard
current loop configuration and tuning components. By adjusting
R1, R2 and C1, the amplifier can be tuned. The value of R1, C1
will vary, depending on the loop bandwidth requirement.
COMMAND IN+, COMMAND IN- ,
COMMAND GROUND, COMMAND OUT
These are the connection pins for the command amplifier. The
command amplifier has a differential input that operates from a
±4Vdc full-scale analog current command.The command ampli-
fier output signal is internally limited to approximately ±5Vdc to
prevent the amplifier from saturating.The input impedance of the
command amplifier is 50K
.
The PW-82520/21N can be used either as a current or voltage
mode controller. When used as a torque controller (current
mode), the input command signal is processed through the com-
mand buffer, which is internally limited to ±5Vdc. The output of
the buffer (command out) is summed with the current monitor
output into the error amplifier. External compensation is used on
the error amp, so the response time can be adjusted to meet the
application.
When used in the voltage mode, the voltage command signal is
applied to the command amplifier, to control the voltage applied
to the motor. The command amplifier output is coupled into the
error amplifier. The error amplifier directly varies the PWM duty
cycle to control the voltage applied to the motor phase. The
nominal PWM frequency in the voltage mode is 50% with zero
volts applied to the command input. The PWM duty cycle is var-
ied by the voltage applied to the command input according to the
transfer function, 12% per volt applied to the command input.The
duty cycle range of the output voltage is limited to approximate-
ly 5-95% in both current and voltage modes.
COMMAND GND
This pin is used when the command buffer is used single-ended and
the COMMAND IN- or COMMAND IN+ are tied to COMMAND GND.
TRANSCONDUCTANCE RATIO AND OFFSET
When the PW-82520/21N is used in the current mode, the com-
mand inputs (COMMAND IN+ and COMMAND IN-) are designed
such that ±4Vdc on either input, with the other input connected
to ground will result in ± full-scale current (Continuous Output
Current: (Ioc) - Refer to TABLE 2) flow into the load. The dc cur-
rent transfer ratio accuracy is ±5% of the rated current including
offset and initial component accuracy. The initial output dc cur-
rent offset with both COMMAND IN+ and COMMAND IN- tied to
the ground will be as shown in TABLE 2 (Ioffset) when measured
using a load of 0.5mH and 1.0W at ambient room temperature
with standard current loop compensation (see FIGURE 8). The
winding phase current error shall be within the cumulative limits
of the transconductance ratio error and the offset error.
R
S
+
Rs+ is the high side of the sense resistor used for non-scaled
test purposes only. Accuracy is not a guaranteed parameter.
OUTPUT CURRENT
Output current derating as a function of the hybrid case temper-
ature is provided in FIGURES 11 and 12. The hybrid contains
internal pulse by pulse current limit circuitry to limit the output
current during fault conditions (See TABLE 2). Current Limit
accuracy is +10/-15%.
WARNING!
The PW-82520/(21)N does not have short cir-
cuit protection.The PW-82520/(21)N must see a minimum of
100μH (400μH) inductive load phase-to-phase or enough
phase-to-phase line-to-line resistance to limit the continuous
output current to less than Ioc at all times. Operation into a
short or a condition that requires excessive output current will
damage the hybrid.
TABLE 4. HALL INPUTS FOR
H-BRIDGE CONTROLLER
INPUTS
OUTPUTS
ENABLE
L
COMMAND IN
Positive
HA
1
HB
1
HC
0
PH B
Z
PH C
L
PH A
H
L
Negative
1
1
0
Z
H
L
H
-
1
1
0
Z
Z
Z
TABLE 3. COMMUTATION TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
DIR*
HA
HB
HC
PHASE
B
L
Z
H
H
Z
L
H
Z
L
L
Z
H
Z
PHASE
C
Z
L
L
Z
H
H
L
L
Z
H
H
Z
Z
PHASE
A
H
H
Z
L
L
Z
Z
H
H
Z
L
L
Z
L
L
L
L
L
L
L
L
L
L
L
L
H
CW
CW
CW
CW
CW
CW
CCW
CCW
CCW
CCW
CCW
CCW
-
1
1
0
0
0
1
1
0
0
0
1
1
-
0
1
1
1
0
0
0
0
1
1
1
0
-
0
0
0
1
1
1
1
1
1
0
0
0
-
1=Logic Voltage >3.5Vdc, 0=Logic voltage < 1.5Vdc
* DIR is based on the convention shown in FIGURE 4.
Actual motor set up might be different.
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