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參數資料
| 型號： | PW-84075P6 |
| 英文描述： | Industrial Control IC |
| 中文描述： | 工業(yè)控制IC |
| 文件頁數： | 4/13頁 |
| 文件大?。?/td> | 196K |
| 代理商： | PW-84075P6 |
INTRODUCTION
The PW-8X075P6 is a universal modular half-bridge motor drive
intended for use with brush, brushless DC and AC induction
motors in aerospace applications.
The isolation barrier, which separates the power and control
stage, attenuates the ground noise generated from high speed,
high power switching. All signals from the control to the power
sections are isolated from power and ground of the other section.
This eliminates false triggering of the input signals and the need
for creative grounding schemes. The isolation barrier also allows
the user to operate the output stage from either unipolar or bipo-
lar power supplies without level shifting the input signals.
A built in power supply located in the control stage provides
power to all electronics in the power stage. This eliminates the
need for refresh cycles or external power supplies for the gate
drive circuitry and allows switching duty cycles from 0 - 100%.
PW-84075P6 provides current sensing of either motor current or
DC bus current. This current signal can be used as a feedback
signal in a servo drive to create a torque loop.
The output power transistors are protected from a short circuit or
overvoltage condition (requires PW-85075P6) applied to the out-
put pins. When a short circuit condition is detected, the output
transistor is shut down and a flag is active indicating a short has
occurred. When an overvoltage condition is detected, the over-
voltage switch is enabled and a external load dump resistor is
connected across the high voltage bus. A status flag is active
indicating an overvoltage condition has occurred.
FUNCTIONAL AND PIN DESCRIPTIONS: (FOR PW-83075P6,
PW-84075P6 AND PW-85075P6 UNLESS NOTED)
UPPER, LOWER
The UPPER and LOWER are CMOS Schmitt-trigger inputs and
control the gate drives of the output transistors. Each input is elec-
trically isolated from the output. A deadband, as shown in FIG-
4
June 13, 2000 Data Device Corporation
MAX
TYP
MIN
SYMBOL
TEST
CONDITION
PARAMETER
TABLE 4. PW-85075P6 SPECIFICATIONS
(TC = +25°C,VCC = VDD = 5V UNLESS OTHERWISE SPECIFIED)
UNITS
Over Voltage Transistor
Continuous Current Drive
Peak Current
Output Voltage Drop (IGBT)
Reverse Leakage @ T
J
= +25°C
Reverse Leakage @ T
J
= +125°C
Over Voltage flyback Diode
Reverse Leakage @ Tc = +25°C
Reverse Leakage @ Tc = +125°C
Over Voltage Trip
Trip Level Hysteresis
Power and Logic Supply
Voltage
Current
Io
I
PEAK
V
CE
(
SAT
)
Ir
Ir
Ir
Ir
Vtrip
Vhyst
+25°C Case
+85°C Case
+85°C Case, 15 ms
600 Vdc
600 Vdc
2.0
35
30
60
3.0
250
1.0
A
A
A
Vdc
μA
mA
480 Vdc
480 Vdc
no external adjustments
370
35
20
1
400
40
50
7
430
45
μA
mA
Vdc
Vdc
THERMAL
Maximum Thermal Resistance
θ
jc
Over Voltage Switch
0.7
0.85
°C/W
5.5
250
5
11
137
4.5
VCC
ICC
Gate Off/ Sleep Mode
25Khz Gate Pulsing
V
mA
mA
URE 2, between UPPER and LOWER inputs is necessary to pre-
vent output cross conduction.
SC FAULT
The SC FAULT output signal indicates when the output of the
motor drive has experienced a short circuit condition. The signal
is normally at a logic high (H). A transition to a logic low (L) will
occur once a short circuit condition is detected. See
SHORT CIR-
CUIT OPERATION
for more detail.
DISABLE / RESET
The DISABLE/RESET control input is CMOS Schmitt-trigger
input and enables (reset) or disables the controller. When the DIS-
ABLE/RESET input receives a logic low (L) pulse for at least 0.1
μs, the SC FAULT output will go high (H) indicating that the inter-
nal circuitry has been enabled or reset. To reset the motor drive,
a logic low (L) must be presented to the DISABLE/RESET inputs
when the AUTO RESET is inactive or at a logic high (H).
AUTO RESET
When the AUTO RESET is tied to SC FAULT, the protection circuit
will reset automatically after the short circuit fault has occurred,
enabling the output to respond to the input commands.
SHORT CIRCUIT OPERATION
for more detail.
See
SHORT CIRCUIT OPERATION
The PW-8X075P6 outputs are completely short-circuit-protected
from either a hard or soft short (required PW-84075 and some
external circuit) to the VBUS+ or VBUS- lines. Each output tran-
sistor is individually short-circuit (hard) protected by circuitry that
detects the desaturation voltage for that transistor during a short
condition. Once a hard short circuit condition is detected, the
active output transistors are shutdown. If the AUTO RESET is
tied to SC FAULT, the circuit will auto reset, remove the short cir-
cuit flag, and reactivate the output transistor within 40 to 100ms.
Vdc
Vdc
K
μs
μs
15.6
0.4
4.8
15
0.2
4.75
36
48
13.8
4.2
I0 = 0
I0 = 0
VOHstatus
VOLstatus
Rstatus
tdon.status
tdoff.status
REGEN STATUS
(ref.to REGEN BUS-)
High Level Output Voltage
Low Level Output Voltage
Output resistance
Vtrip rise to status ON Delay
Vtrip fall status OFF Delay
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