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參數(shù)資料
| 型號： | PWS740 |
| 英文描述： | Distributed Multi-Channel Isolated DC-TO-DC CONVERTER |
| 中文描述： | 分布式多通道隔離型DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 117K |
| 代理商： | PWS740 |
6
PWS740
If larger temperature gradients are likely to occur, the user
may wish to consider the synchronization method shown in
Figure 2. This circuit is driven from an external TTL-
compatible source such as a system clock or a simple free-
running oscillator constructed of TTL gates. The output
stage provides temperature compensation over the rated
temperature range of the PWS740. The signal source fre-
quency should be about 800kHz for rated performance, but
may range from 500kHz to 2MHz with slightly reduced
performance. Precautions with regard to circuit coupling and
layout are the same as for the circuit of Figure 1. Repeaters
using the OPA633 may be used for long line lengths.
Symmetry and good high-frequency layout practice are
important in successful application of both of these synchro-
nization techniques.
FREQUENCY ADJUSTMENT
The FREQ ADJ pin may be connected to an external
potentiometer to lower an unsynchronized PWS740-1 oscil-
lator frequency. This may be useful if the frequency of the
PWS740-1 is too close to some other signal’s frequency in
the system and beat interference is possible. See Typical
Performance Curves. Use of this pin is not usually required;
if not used, leave open for rated performance.
THEORY OF OPERATION
EXTERNAL FILTER COMPONENTS
Filter components are necessary to reduce the input ripple
current and the output voltage noise. Without any input
filtering, the sawtooth currents in the FET switches would
flow in the +V supply line. Since this AC current can be as
great as 1A peak, voltage interference with other compo-
nents using this supply line would likely occur. The input
ripple current can be reduced to approximately 1mA peak
FIGURE 2. External Synchronization of Multiple PWS740 Drivers with TTL-Level Signals.
1/8W
TTL Sync
(1)
+5V
8
1
2
4
3
330
1W
+V (7-20V)
2N3904
620
100
2.5V
(2)
4.0V
200ns
2
2
Other
PWS740s
1
1
Other
PWS740s
PWS740-1
PWS740-1
Peripheral
Driver
(MC1472 or
Equivalent)
2N3904
NOTES: (1) See text for frequency range; duty cycle = 5-75%. (2) Typical waveform at 25
°
C. Active
pull-up initiates synchronization; pulse width is set by PWS740 pull-down characteristics and is not
affected by frequency of operation.
(2) Pulse Engineering, PO Box 12235, San Diego CA 92112, 619-268-2400.
with the addition of two components—a bypass capacitor
between the +V
IN
pin and ground, and a series inductor in the
V
DRIVE
line. A 10
μ
F tantalum capacitor is adequate for
bypass. A parallel 0.33
μ
F ceramic capacitor will extend the
bandwidth of the tantalum. Additional bypass capacitors at
each primary center-tap of the transformers are recom-
mended. In general, the higher the capacitance, the lower the
ripple, but the parasitic series inductance of the bypass
capacitors will eventually be the limiting factor. The induc-
tor value recommended is approximately 20
μ
H. Greater
reduction in ripple current is achieved with values up to
100
μ
H; then physical size may become a concern. The
inductor should be rated for at least 2A and its DC resistance
should be less than 0.1
. An example of a low cost indicator
is part number 51591 from Pulse Engineering
(2)
.
Output voltage filtering is achieved with a 0.33
μ
F capacitor
connecting each V
OUT
pin of the diode bridge to ground.
Short leads and close placement of the capacitors to the unit
provide optimum high frequency bypassing. The 800kHz
output ripple should be below 5mVp-p. Higher frequency
noise bursts are also present at the outputs. They coincide
with the switch times and are approximately 20mV in ampli-
tude. Inductance of 10
μ
H or less in series with the output
loads will significantly reduce the noise as seen by the loads.
PC BOARD LAYOUT CONSIDERATIONS
Multilayer printed circuit boards are recommended for
PWS740 systems. Two-layer boards are certainly possible
with satisfactory operation; however, three layers provide
greater density and better control of interference from the
FET switch signals. Should four-layer boards be required for
other circuitry, the use of separate layers for power and
ground planes, a layer for switching signals, and a layer for
analog signals would allow the most straightforward layout
for the PWS740 system. The following discussion pertains
to a three- or four-layer board layout.
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