參數(shù)資料
型號(hào): PXA210
廠商: Intel Corp.
英文描述: Intel-R PXA250 and PXA210 Applications Processors
中文描述: 英特爾- R的PXA250和PXA210應(yīng)用處理器
文件頁數(shù): 44/46頁
文件大?。?/td> 431K
代理商: PXA210
PXA250 and PXA210
Electrical, Mechanical, and Thermal Specification
44
Datasheet
4.8.3
Boundary Scan Test Signal Timings
Boundary scan test signal timing is shown in Table 23,
Boundary Scan Test Signal Timing
.
Figure 9. SSP AC Timing Definitions
Table 22. SSP AC Timing Specifications
Symbol
Description
Min
Max
Units
Notes
Tsfmv
SCLK_C rise to SFRM_C driven valid
21
ns
Trxds
RXD_C valid to SCLK_C fall (input setup)
11
ns
Trxdh
SCLK_C fall to RXD_C invalid (input
hold)
0
ns
Tsfmv
SCLK_C rise to TXD_C valid
22
ns
A4774-01
SCLK_C
SFRM_C
TXD_C
RXD_C
Tsfmv
Tsfmv
Trxds
Trxdh
Table 23. Boundary Scan Test Signal Timing (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
Notes
TBSF
TCK Frequency
0.0
33.33
MHz
TBSCH
TCK High Time
15.0
ns
Measured at 1.5 V
TBSCL
TCK Low Time
15.0
ns
Measured at 1.5 V
TBSCR
TCK Rise Time
5.0
ns
0.8 V to 2.0 V
TBSCF
TCK Fall Time
5.0
ns
2.0 V to 0.8 V
TBSIS1
Input Setup to TCK TDI, TMS
4.0
ns
TBSIH1
Input Hold from TCK TDI, TMS
6.0
ns
TBSIS2
Input Setup to TCK nTRST
25.0
ns
TBSIH2
Input Hold from TCK nTRST
3.0
ns
TBSOV1
TDO Valid Delay
1.5
6.9
ns
Relative to falling edge of TCK
TOF1
TDO Float Delay
1.1
5.4
ns
Relative to falling edge of TCK
TOV12
All Outputs (Non-Test) Valid
Delay
1.5
6.9
ns
Relative to falling edge of TCK
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