參數(shù)資料
型號(hào)： PXA270
廠商： Intel Corp.
英文描述： Electrical, Mechanical, and Thermal Specification
中文描述： 電氣，機(jī)械和熱規(guī)格
文件頁數(shù)： 48/126頁
文件大?。?/td> 1563K
代理商： PXA270
4-28
Electrical, Mechanical, and Thermal Specification
Intel PXA270 Processor
Pin Listing and Signal Definitions
4.4
Memory Controller Reset and Initialization
On reset, the SDRAM interface is disabled. Reset values for the boot ROM are determined by
BOOT_SEL (see the
Intel PXA27x Processor Family Developers Manual
, Memory Controller
chapter). Boot ROM is immediately available for reading upon exit from reset, and all memory
interface control registers are available for writing.
On hardware reset, the memory pins and controller are in the state shown in
Table 4-4
.
Table 4-3. Signal Types
Type
Description
IC
CMOS input
OC
CMOS output
OCZ
CMOS output, three-stateable
ICOCZ
CMOS bidirectional, three-stateable
IA
Analog input
OA
Analog output
IAOA
Analog bidirectional
IAOAZ
Analog bidirectional - three-stateable
PS
Power supply
Table 4-4. Memory Controller Pin Reset Values (Sheet 1 of 2)
Pin Name
Reset, Sleep, Standby, Deep-Sleep, Frequency
Change, and Manual Self-Refresh Mode Values
SDCLK <3
1
:0>
0b000
SDCKE
0
DQM <3:0>
0b0000
nSDCS <3:2>
GPIO (memory controller drives 0b11)
nSDCS <1:0>
0b11
nWE
1
nSDRAS
1
nSDCAS
1
nOE
1
MA <25:0>
0x0000_0000
1
RDnWR
0
MD <31:0>
0x0000_0000
2
nCS <0>
1
nCS <5:1>
GPIO (memory controller drives 0b11111)
nPIOIR
GPIO (memory controller drives high)
nPIOIW
GPIO (memory controller drives high)
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