參數資料
型號： PXASCCKFBE
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CMOS 16-bit communications microcontroller
中文描述： 16-BIT, 30 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100
文件頁數： 22/42頁
文件大小： 229K
代理商： PXASCCKFBE
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
22
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached SCCs. These modes are
summarized in the following table. For full details on implementation
and use, see the XA-SCC User Manual.
Table 5. Rx DMA Modes Summary
Mode
Byte Count Source
Maskable Interrupt
Description
SDLC/HDLC Rx
Chaining
DMA stores byte count in header in
memory with data packet.
At end of received
packet
When a complete or aborted SDLC/HDLC
packet has been received, the packet byte count
and status information are stored in memory with
the packet. A maskable interrupt is generated.
Periodic Interrupt
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
When Byte Counter
reaches zero and is
reloaded by DMA
hardware from the byte
count register.
The DMA channel runs until commanded to stop
by the processor. It generates a maskable
interrupt once per n bytes, where n is the
number written once into the byte count register
by the processor, thus an interrupt is generated
once every n received bytes.
Processor specifies time out period between
incoming characters. If no character is received
within that time, interrupt is generated.
Asynchronous
Character Time Out
Byte Count can be calculated by
software from the DMA address
pointer.
If no character is
received within a
specified time out
period, then interrupt.
Asynchronous
Character Match
Byte Count can be calculated by
software from the DMA address
pointer.
When matched
character is stored in
memory.
There are four match registers, each incoming
character is compared to all four registers. When
a matched character is stored in memory by
DMA, a maskable interrupt is generated.
SU01127
DATA FIFO 3
DATA FIFO 2
DATA FIFO 1
DATA FIFO 0
Rx TIME OUT
FIFO CONTROL
DMA CONTROL
SEGMENT
BUFFER BASE
BUFFER BOUND
ADDRESS POINTER
BYTE COUNT
DATA FIFO 3
DATA FIFO 2
DATA FIFO 1
DATA FIFO 0
FIFO CONTROL
DMA CONTROL
SEGMENT
BUFFER BASE
BUFFER BOUND
ADDRESS POINTER
BYTE COUNT
Rx CHANNEL
Tx CHANNEL
Figure 6. Rx and Tx DMA Registers
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