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參數(shù)資料
| 型號(hào)： | PZ128-S12A84 |
| 英文描述： | IC-SM-CMOS PLD |
| 中文描述： | 集成電路釤的CMOS可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | PZ128-S12A84 |
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R
XCR3128: 128 Macrocell CPLD
DS034 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
6
This product has been discontinued. Please see
for details.JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of spe-
cialized test equipment. BST provides the ability to test the
external connections of a device, test the internal logic of
the device, and capture data from the device during normal
operation. BST provides a number of benefits in each of the
following areas:
Testability
-
Allows testing of an unlimited number of
interconnects on the printed circuit board
-
Testability is designed in at the component level
-
Enables desired signal levels to be set at specific
pins (Preload)
-
Data from pin or core logic signals can be examined
during normal operation
Reliability
-
Eliminates physical contacts common to existing test
fixtures (e.g., "bed-of-nails")
-
Degradation of test equipment is no longer a
concern
-
Facilitates the handling of smaller, surface-mount
components
-
Allows for testing when components exist on both
sides of the printed circuit board
Cost
-
Reduces/eliminates the need for expensive test
equipment
-
Reduces test preparation time
-
Reduces spare board inventories
The Xilinx XCR3128's JTAG interface includes a TAP Port
and a TAP Controller, both of which are defined by the IEEE
1149.1 JTAG Specification. As implemented in the Xilinx
Figure 5: I
CC
vs. Frequency @ V
CC
= 3.3V, 25°C
Table 1: I
CC
vs. Frequency
(V
CC
= 3.3V, 25
°
C)
Frequency (MHz)
Typical I
CC
(mA)
0
1
20
12
40
24
60
35
80
46
100
63
.03
.06
FREQUENCY (MHz)
SP00471
0
20
40
60
80
0
20
40
60
80
100
120
140
I
(mA)
100
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