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| 型號： | PZ3128-S10BB1 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 161K |
| 代理商： | PZ3128-S10BB1 |
R
XCR3128: 128 Macrocell CPLD
DS034 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
10
This product has been discontinued. Please see
for details.Absolute Maximum Ratings
1
Operating Range
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0
°
C
≤
T
AMB
≤
+70
°
C; 3.0V
≤
V
CC
≤
3.6V
Symbol
V
CC
V
I
V
OUT
I
IN
I
OUT
T
J
T
str
Parameter
Min.
-0.5
Max.
7.0
Unit
V
Supply voltage
2
Input voltage
Output voltage
Input current
Output current
Maximum junction temperature
Storage temperature
-1.2
-0.5
-30
-100
-40
-65
V
CC
+ 0.5
V
CC
+ 0.5
30
100
150
150
V
V
mA
mA
°
C
°
C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Product Grade
Commercial
Industrial
Temperature
0 to +70
°
C
-40 to +85
°
C
Voltage
3.3V
±
10%
3.3V ± 10%
Symbol
V
IL
V
IH
V
I
V
OL
V
OH
I
I
I
OZ
I
CCQ1
I
CCD1, 2
Parameter
Test Conditions
Min.
Max.
0.8
Unit
V
V
V
V
V
μ
A
μ
A
μ
A
mA
mA
mA
Input voltage low
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
Input leakage current
3-stated output leakage current
Standby current
Dynamic current
V
CC
= 3.0V
V
CC
= 3.6V
V
CC
= 3.0V, I
IN
= -18 mA
V
CC =
3.0V, I
OL
= 8 mA
V
CC
= 3.0V, I
OH
= -8 mA
V
IN
= 0 to V
CC
V
IN
= 0 to V
CC
V
CC
= 3.6V, T
AMB
= 0
°
C
V
CC
= 3.6V, T
AMB
= 0
°
C at 1 MHz
V
CC
= 3.6V, T
AMB
= 0
°
C at 50 MHz
One pin at a time for no longer than 1
second
T
AMB
= 25
°
C, f = 1 MHz
T
AMB
= 25
°
C, f = 1MHz
T
AMB
= 25
°
C, f = 1MHz
2.0
-1.2
0.5
2.4
-10
-10
10
10
60
2
50
-100
I
OS
Short circuit output current
3
-50
C
IN
C
CLK
C
I/O
Notes:
Input pin capacitance
3
Clock input capacitance
3
I/O pin capacitance
3
8
pF
pF
pF
5
12
10
1. See
Table 1 on page 6
for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
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