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參數(shù)資料
| 型號(hào)： | PZ3128-S12BB2 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | PZ3128-S12BB2 |
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R
XCR3128: 128 Macrocell CPLD
DS034 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
8
This product has been discontinued. Please see
for details.3.3V In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Design
-
Faster time-to-market
-
Debug partitioning and simplified prototyping
-
Printed circuit board reconfiguration during debug
-
Better device and board level testing
Manufacturing
-
Multi-Functional hardware
-
Reconfigurability for test
-
Eliminates handling of "fine lead-pitch" components
for programming
-
Reduced Inventory and manufacturing costs
-
Improved quality and reliability
Field Support
-
Easy remote upgrades and repair
-
Support for field configuration, re-configuration, and
customization
The Xilinx XCR3128 allows for 3.3V, in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR3128
may be easily programmed on the circuit board using only
the 3.3-volt supply required by the device for normal oper-
ation. A set of low-level ISP basic commands implemented
in the XCR3128 enable this feature. The ISP commands
implemented in the Xilinx XCR3128 are specified in
Table 5
Please note that an ENABLE command must precede all
ISP commands
unless
an ENABLE command has already
been given for a preceding ISP command
and
the device
has not gone through a Test-Logic/Rest TAP Controller
State. See also
Table 5
Programming Specifications.
Table 4: XCR3128 Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
Sample/Preload
(0010)
Boundary-Scan Register
Description
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal
operation of the component to be taken and examined. It also allows data values to
be loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register
prior to selection of the other boundary-scan test instructions.
The mandatory EXTEST instruction allows testing of off-chip circuitry and board
level interconnections. Data would typically be loaded onto the latched parallel
outputs of Boundary-Scan Shift-Register using the Sample/Preload instruction prior
to selection of the EXTEST instruction.
Places the 1 bit bypass register between the TDI and TDO pins, which allows the
BST data to pass synchronously through the selected device to adjacent devices
during normal device operation. The Bypass instruction can be entered by holding
TDI at a constant high value and completing an Instruction-Scan cycle.
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind
interrogation of the components assembled onto a printed circuit board. Thus, in
circumstances where the component population may vary, it is possible to deter-
mine what components exist in a product.
The HIGHZ instruction places the component in a state in which all of its system
logic outputs are placed in an inactive drive state (e.g., high impedance). In this
state, an in-circuit test system may drive signals onto the connections normally
driven by a component output without incurring the risk of damage to the compo-
nent. The HighZ instruction also forces the Bypass Register between TDI and TDO.
Extest
(0000)
Boundary-Scan Register
Bypass
(1111)
Bypass Register
Idcode
(0001)
Boundary-Scan Register
HighZ
(0101)
Bypass Register
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