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參數資料
| 型號： | PZ3128IS15BE |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復雜可編程邏輯器件 |
| 文件頁數： | 3/18頁 |
| 文件大?。?/td> | 161K |
| 代理商： | PZ3128IS15BE |
R
XCR3128: 128 Macrocell CPLD
3
www.xilinx.com
1-800-255-7778
DS034 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Logic Block Architecture
Figure 2
illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. the six control terms can individually be con-
figured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 mac-
rocells
’
flip-flops. The PAL array consists of a programma-
ble AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programma-
ble OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
PD
of the XCR3128 device
through the PAL array is 10 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 2.5 ns.
So the total pin-to-pin t
PD
for the XCR3128 using six to 37
product terms is 12.5 ns (10 ns for the PAL + 2.5 ns for the
PLA).
Figure 2: Xilinx XPLA Logic Block Architecture
T
6
5
CONTROL
PAL
ARRAY
36 ZIA INPUTS
PLA
ARRAY
(32)
SP00435A
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