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| 型號(hào)： | PZ3128IS15BP-S |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | PZ3128IS15BP-S |
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R
XCR3128: 128 Macrocell CPLD
5
www.xilinx.com
1-800-255-7778
DS034 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Simple Timing Model
Figure 4
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
PD
, t
SU
, and t
CO
. In other competing architec-
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This
is because the timing models of competing architectures
are very complex and include such things as timing depen-
dencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
TotalCMOS
Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of our XCR3128 TotalCMOS CPLD (data taken
w/eight up/down, loadable 16 bit counters at 3.3V, 25
°
C).
Figure 4: CoolRunner Timing Model
OUTPUT PIN
INPUT PIN
SP00441
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
GLOBAL CLOCK PIN
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