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參數(shù)資料
| 型號： | Q67037-A1162 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MB 26C 26#20 PIN PLUG |
| 中文描述： | 2波段電視調(diào)諧器混頻器振蕩器鎖相環(huán)不平衡中頻放大器 |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 687K |
| 代理商： | Q67037-A1162 |
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Functional Description
3 - 18
KTS6027-2, KTS6029-2
Wireless Components
Specification, July 2001
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table
”
Bit Allocation
”
(
see Table 5-4 Bit Allocation Read / Write on page 31
) should be
referred to the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA
line to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (
see
Table 5-6 Address selection on page 32
).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when V
CC
falls below 3.2 V. It will be reset
at the end of a READ operation.
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