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參數(shù)資料
| 型號(hào)： | Q67040-S4001-A2 |
| 廠(chǎng)商： | SIEMENS AG |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | High Speed CMOS Logic 7-Stage Binary Ripple Counter 14-TSSOP -55 to 125 |
| 中文描述： | SIPMOS功率晶體管（N通道增強(qiáng)模式雪崩額定dv / dt的評(píng)價(jià)） |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | Q67040-S4001-A2 |
Semiconductor Group
3
30/Jan/1998
BUZ 100 S
SPP77N05
Electrical Characteristics,
at
T
j
= 25°C, unless otherwise specified
Parameter
Symbol
Values
Unit
min.
typ.
max.
Dynamic Characteristics
Transconductance
V
DS
≥
2
*
I
D *
R
DS(on)max,
I
D
= 55 A
Input capacitance
g
fs
25
-
-
S
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Output capacitance
C
iss
-
1900
2375
pF
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Reverse transfer capacitance
C
oss
-
615
770
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Turn-on delay time
C
rss
-
310
390
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 77 A
R
G
= 4.7
Rise time
t
d(on)
-
15
25
ns
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 77 A
R
G
= 4.7
Turn-off delay time
t
r
-
30
45
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 77 A
R
G
= 4.7
Fall time
t
d(off)
-
40
60
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 77 A
R
G
= 4.7
Gate charge at threshold
t
f
-
25
40
V
DD
= 40 V,
I
D
= 0.1 A,
V
GS
=0 to 1 V
Gate charge at 7.0 V
Q
g(th)
-
2.5
3.8
nC
V
DD
= 40 V,
I
D
= 77 A,
V
GS
=0 to 7 V
Gate charge total
Q
g(7)
-
50
75
V
DD
= 40 V,
I
D
= 77 A,
V
GS
=0 to 10 V
Gate plateau voltage
Q
g(total)
-
65
100
V
DD
= 40 V,
I
D
= 77 A
V
(plateau)
-
5.9
-
V
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