參數(shù)資料
型號: Q67040-S4010-A2
廠商: SIEMENS AG
元件分類: 通用總線功能
英文描述: High Speed CMOS Logic 12-Stage Binary Counter 16-PDIP -55 to 125
中文描述: SIPMOS功率晶體管(N通道增強(qiáng)模式的邏輯電平雪崩額定dv / dt的評價(jià))
文件頁數(shù): 3/8頁
文件大小: 120K
代理商: Q67040-S4010-A2
Semiconductor Group
3
30/Jan/1998
BUZ 102 SL
SPP47N05L
Electrical Characteristics,
at
T
j
= 25°C, unless otherwise specified
Parameter
Symbol
Values
Unit
min.
typ.
max.
Dynamic Characteristics
Transconductance
V
DS
2
*
I
D *
R
DS(on)max,
I
D
= 33 A
Input capacitance
g
fs
10
-
-
S
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Output capacitance
C
iss
-
1380
1730
pF
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Reverse transfer capacitance
C
oss
-
410
515
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Turn-on delay time
C
rss
-
230
290
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 47 A
R
G
= 3.6
Rise time
t
d(on)
-
15
25
ns
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 47 A
R
G
= 3.6
Turn-off delay time
t
r
-
30
45
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 47 A
R
G
= 3.6
Fall time
t
d(off)
-
30
45
V
DD
= 30 V,
V
GS
= 4.5 V,
I
D
= 47 A
R
G
= 3.6
Gate charge at threshold
t
f
-
20
30
V
DD
= 40 V,
I
D
= 0.1 A,
V
GS
=0 to 1 V
Gate charge at 5.0 V
Q
g(th)
-
2
3
nC
V
DD
= 40 V,
I
D
= 47 A,
V
GS
=0 to 5 V
Gate charge total
Q
g(5)
-
35
55
V
DD
= 40 V,
I
D
= 47 A,
V
GS
=0 to 10 V
Gate plateau voltage
Q
g(total)
-
60
90
V
DD
= 40 V,
I
D
= 47 A
V
(plateau)
-
4.1
-
V
相關(guān)PDF資料
PDF描述
Q67040-S4011-A2 High Speed CMOS Logic 12-Stage Binary Counter 16-SOIC -55 to 125
Q67040-S4012-A2 High Speed CMOS Logic 12-Stage Binary Counter 16-SOIC -55 to 125
Q67040-S4013-A2 High Speed CMOS Logic 12-Stage Binary Counter 16-SOIC -55 to 125
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