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參數(shù)資料
| 型號(hào)： | Q67040-S4124-A2 |
| 廠商： | SIEMENS AG |
| 英文描述： | SIPMOS Power Transistor |
| 中文描述： | SIPMOS功率晶體管 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 139K |
| 代理商： | Q67040-S4124-A2 |
Semiconductor Group
1
29/Jan/1998
SPD13N05L
SPU13N05
L
SIPMOS
Power Transistor
N channel
Enhancement mode
Logic Level
Avalanche-rated
d
v
/d
t
rated
175°C operating temperature
Pin 1
Pin 2
Pin 3
G
D
S
Type
V
DS
55 V
I
D
12.5 A
R
DS(on
)
0.12
0.12
Package
Ordering Code
SPD13N05L
P-TO252
Q67040 - S4124 - A2
SPU13N05L
55 V
12.5 A
P-TO251
Q67040 - S4116 - A2
Maximum Ratings
Parameter
Symbol
Values
Unit
Continuous drain current
T
C
= 25 °C
T
C
= 100 °C
Pulsed drain current
I
D
8.8
12.5
A
T
C
= 25 °C
Avalanche energy, single pulse
I
Dpuls
50
I
D
= 12.5 A,
V
DD
= 25 V,
R
GS
= 25
L
= 666 μH,
T
j
= 25 °C
Avalanche current,limited by
T
jmax
Avalanche energy,periodic limited by
T
jmax
Reverse diode d
v
/d
t
E
AS
52
mJ
I
AR
E
AR
d
v
/d
t
12.5
A
3.5
mJ
I
S
= 12.5 A,
V
DS
= 40 V, d
i
F
/d
t
= 200 A/μs
T
jmax
= 175 °C
Gate source voltage
6
±
14
kV/μs
V
GS
P
tot
V
Power dissipation
T
C
= 25 °C
35
W
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