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參數(shù)資料
| 型號： | Q67040-S4138-A2 |
| 廠商： | SIEMENS AG |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed CMOS Logic 12-Stage Binary Counter 16-SO -55 to 125 |
| 中文描述： | SIPMOS功率晶體管 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 148K |
| 代理商： | Q67040-S4138-A2 |
Semiconductor Group
3
29/Jan/1998
SPD23N05
SPU23N05
Electrical Characteristics,
at
T
j
= 25°C, unless otherwise specified
Parameter
Symbol
Values
Unit
min.
typ.
max.
Dynamic Characteristics
Transconductance
V
DS
≥
2
*
I
D *
R
DS(on)max,
I
D
= 16 A
Input capacitance
g
fs
7
10
-
S
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Output capacitance
C
iss
-
490
615
pF
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Reverse transfer capacitance
C
oss
-
170
215
V
GS
= 0 V,
V
DS
= 25 V,
f
= 1 MHz
Turn-on delay time
C
rss
-
95
120
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 22 A
R
G
= 20
Rise time
t
d(on)
-
15
25
ns
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 22 A
R
G
= 20
Turn-off delay time
t
r
-
25
40
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 22 A
R
G
= 20
Fall time
t
d(off)
-
30
45
V
DD
= 30 V,
V
GS
= 10 V,
I
D
= 22 A
R
G
= 20
Gate charge at threshold
t
f
-
25
40
V
DD
= 40 V,
I
D
= 0.1 A,
V
GS
=0 to 1 V
Gate charge at 7.0 V
Q
g(th)
-
0.5
0.75
nC
V
DD
= 40 V,
I
D
= 22 A,
V
GS
=0 to 7 V
Gate charge total
Q
g(7)
-
13
20
V
DD
= 40 V,
I
D
= 22 A,
V
GS
=0 to 10 V
Gate plateau voltage
Q
g(total)
-
17
26
V
DD
= 40 V,
I
D
= 22 A
V
(plateau)
-
5.9
-
V
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