參數(shù)資料
型號: Q67100-A6059
廠商: SIEMENS AG
英文描述: Primary Rate Access Clock Generator and Transceiver PRACT
中文描述: 主速率接入時鐘發(fā)生器和收發(fā)PRACT
文件頁數(shù): 33/53頁
文件大?。?/td> 418K
代理商: Q67100-A6059
HYB39S64400/800/160BT(L)
64MBit Synchronous DRAM
Semiconductor Group
32
11. Power on Sequence and Auto Refresh (CBR)
Inputs must be
stable for
200
μ
s
DQM
AP
DQ
Addr.
BS
RP
Command
All Banks
Precharge
Hi-Z
~
t
1st Auto Refresh
Command
~
~
~
~
~
~
~
SPT03913
Mode Register
Set Command
Address Key
8th Auto Refresh
Command
~
t
RC
~
~
~
~
~
~
~
Command
Any
Minimum of 8 Refresh Cycles are required
T8
WE
CAS
RAS
CS
CKE
CLK
required
~
~
~
~
~
~
~
T3
is
~
~
Level
High
T0
T2
T1
T5
T4
T7
T6
T18
2 Clock min.
~
~
~
~
~
~
~
T13
~
~
T10
T9
T12
T11
T14
T15
T17
T16
T20
T19
T22
T21
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