參數(shù)資料
型號: Q67100-H5092
廠商: SIEMENS AG
英文描述: Nonvolatile Memory 1-Kbit E2PROM
中文描述: 非易失性內(nèi)存的1 - kbit E2PROM的
文件頁數(shù): 9/53頁
文件大?。?/td> 418K
代理商: Q67100-H5092
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
9
12.99
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Notes
1.
V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode
cycle device is clock suspend mode.
Operation
Device
State
Idle
3
Active
3
Active
3
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM A0-9,
A11
A10
BA0
BA1
Row Activate (ACT)
H
X
L
L
H
H
X
V
V
V
Read (READ)
H
X
L
H
L
H
X
V
L
V
Read w/ Autoprecharge
(READA)
H
X
L
H
L
H
X
V
H
V
Write (WRITE)
Active
3
Active
3
H
X
L
H
L
L
X
V
L
V
Write w/ Autoprecharge
(WRITEA)
H
X
L
H
L
L
X
V
H
V
Row Precharge (PRE)
Any
H
X
L
L
H
L
X
X
L
V
Precharge All (PREA)
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set (MRS)
Idle
H
X
L
L
L
L
X
V
V
V
No Operation (NOP)
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect (INHBT)
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh (REFA)
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry (REFS-EN) Idle
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit (REFS-EX)
Idle
(Self
Refr.)
L
H
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Entry (PDN-EN) Idle
Active
5
H
L
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Exit (PDN-EX)
Any
(Power
Down)
L
H
H
X
X
X
X
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
相關(guān)PDF資料
PDF描述
Q67100-H5095 Nonvolatile Memory 2-Kbit E2PROM with I2C Bus
Q67100-H5139 PLL with I2C Bus for AM/FM Receivers
Q67100-H5148 Quarter PIP Processor
Q67100-H5156 Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
Q67100-H5164 VPS / PDC-plus Decoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Q67100-H5095 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Nonvolatile Memory 2-Kbit E2PROM with I2C Bus
Q67100-H5096 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface
Q67100-H5101 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:NONVOLATILE MEMORY 8-KBIT EPROM WITH IC BUS INTERFACE
Q67100-H5139 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:PLL with I2C Bus for AM/FM Receivers
Q67100-H5142 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Picture-in-Picture Processor with On-Chip PLL