參數(shù)資料
型號： Q67100-H5156
廠商： SIEMENS AG
英文描述： Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
中文描述： 擴(kuò)大解碼器程序化控制和視頻點(diǎn)播系統(tǒng)的EPDC /車輛定位系統(tǒng)解碼器
文件頁數(shù)： 13/53頁
文件大?。?/td> 418K
代理商： Q67100-H5156
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
13
12.99
command is necessary. A minimum
t
RC
time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one
t
RC
delay is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency
t
DQZ
). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency
t
DQW
= zero clocks).
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency
t
CSL
).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be
precharged and the necessary Precharge delay (
t
RP
) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver
circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh
operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
(
t
REF
) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is
required for mode entry and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the
Read with Auto-Precharge
function is initiated. If CA10 is high when a Write Command is issued, the
Write with Auto-
Precharge
function is initiated. The SDRAM automatically enters the precharge operation two
clocks after the last data in.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay
t
WR
from the last data out to apply the precharge command.
相關(guān)PDF資料
PDF描述
Q67100-H5164 VPS / PDC-plus Decoder
Q67100-H5182 VPS-Decoder
Q67100-H6032 General-Purpose Power Controller
Q67100-H6209 Multipoint Switching and Conferencing Unit - Attenuation MUSAC
Q67100-H6238 Memory Time Switch Large MTSL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Q67100-H5164 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS / PDC-plus Decoder
Q67100-H5182 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS-Decoder
Q67100-H6032 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:General-Purpose Power Controller
Q67100-H6035 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ICs for Communications
Q67100-H6055 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch CMOS (MTSC)
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