參數(shù)資料
型號: Q67120-C494
廠商: SIEMENS AG
英文描述: High Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry 16-SOIC -55 to 125
中文描述: 高速CMOS邏輯4位二進制快速進位全加法器 SOIC-16封裝 工作溫度:-55℃_125℃
文件頁數(shù): 16/24頁
文件大?。?/td> 980K
代理商: Q67120-C494
C167CS-xC Bare Die
Step BA
Data Sheet
12
V1.0, 2001-08
Note: All
SS
pads and all
power supply, respectively.
The pad definitions and locations in this table are only valid for the indicated device
and design step.
DD
pads must be connected to the system ground and the
P7.6
135
I/O
0
2174 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC30IO.
1990 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC31IO.
1701 Port 5 input, analog input AN0.
1546 Port 5 input, analog input AN1.
1391 Port 5 input, analog input AN2.
1236 Port 5 input, analog input AN3.
1081 Port 5 input, analog input AN4.
925 Port 5 input, analog input AN5.
770 Port 5 input, analog input AN6.
615 Port 5 input, analog input AN7.
460 Port 5 input, analog input AN8.
305 Port 5 input, analog input AN9.
P7.7
136
I/O
0
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
137
138
139
140
141
142
143
144
145
146
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
0
0
0
1)
Prepared to enable Enhanced Mode, i.e. low-power oscillator mode, single-chip reset with RD/ALE-
configuration.
Table 2
Pad Definitions and Functions
(cont
d)
Symbol Pad
Num
In /
Out
Position
[μm]
Function
x
y
相關PDF資料
PDF描述
Q67120-C517 High Speed CMOS Logic Digital Phase-Locked-Loop 16-PDIP -55 to 125
Q67120-C552 High Speed CMOS Logic Digital Phase-Locked-Loop 16-PDIP -55 to 125
Q67120-C556 High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs 20-PDIP -55 to 125
Q67120-C557 High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs 20-SOIC -55 to 125
Q67120-C582 High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs 20-SOIC -55 to 125
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