參數(shù)資料
型號(hào)： QL1P100-7PUN86M
廠商： QUICKLOGIC CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 640 CLBS, 100000 GATES, PBGA86
封裝： 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86
文件頁(yè)數(shù)： 7/44頁(yè)
文件大?。?/td> 1101K
代理商： QL1P100-7PUN86M
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
15
CCM Configurations
The main purpose of the CCM is to align the clock arrival times of two separate clock destinations, whether
it is within the FPGA or external to the chip. The difference between the two clock destinations is referred to
as clock skew. To correct for clock skew the CCMs can be configured to shift the phase and/or delay of the
pllout1 clock output.
In most cases the desired phase or added delay can be accomplished by configuring both the clock source input
and feedback input as dedicated. In the case of a dedicated clock source and dedicated feedback, the
QuickLogic development software calculates and generates all of the required routing delays to produce the
requested configuration.
For more information on CCMs and how to use them in QuickWorks, refer to Application Note 87
Configurable Clock Managers.
Table 15: Time Delay Control Values
tdctl[3:0]
Time Delay
(ps)
0000
0
0001
250
0010
500
0011
750
0100
1000
0101
1250
0110
1500
0111
1750
1000
2000
1001
2250
1010
2500
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Table 16: Available Configurations
Clock
Feedback
Example Usage
Comments
Dedicated
clock pad
Dedicated
feedback
Standard PLL application. Reduce set-up or
clock-to-out time.
If the clock pad and destination are
in phase.
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