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| 型號(hào)： | QL3006-0PFN100I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 160 CLBS, 6000 GATES, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MO-136, TQFP-100 |
| 文件頁數(shù)： | 2/49頁 |
| 文件大小： | 885K |
| 代理商： | QL3006-0PFN100I |
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www.quicklogic.com
2005 QuickLogic Corporation
pASIC 3 FPGA Family Data Sheet Rev. D
10
Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the
data passes through the bypass register. The Bypass instruction allows users to test a device without passing
through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data
to be transferred through a device without affecting the operation of the device.
Pin Descriptions
Table 11: Pin Descriptions
Pin
Function
Description
TDI
Test data in for JTAG
Hold HIGH during normal operation. Connect to V
CC if not
used for JTAG.
TRSTB
Active low reset for JTAG
Hold LOW during normal operation. Connect to ground if not
used for JTAG.
TMS
Test mode select for JTAG
Hold HIGH during normal operation. Connect to VCC if not
used for JTAG.
TCK
Test clock for JTAG
Hold HIGH or LOW during normal operation. Connect to V
CC
or ground if not used for JTAG.
TDO
Test data out for JTAG
Output that must be left unconnected if not used for JTAG.
STM
Special test mode
Must be grounded during normal operation.
I/ACLK
High-drive input and/or array network
driver
Can be configured as either or both.
I/GCLK
High-drive input and/or global
network driver
Can be configured as either or both.
I
High-drive input
Use for input signals with high fanout.
I/O
Input/output pin
Can be configured as an input and/or output.
V
CC
Power supply pin
Connect to 3.3 V supply.
VCCIO
Input voltage tolerance pin
Connect to 5.0 V supply if 5.0 V input tolerance is required,
otherwise connect to 3.3 V supply.
GND
Ground pin
Connect to ground.
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