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參數(shù)資料
| 型號： | QL4058-0PBN456I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034BAR-2, BGA-456 |
| 文件頁數(shù)： | 4/45頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | QL4058-0PBN456I |
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2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
12
Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the
data passes through the bypass register. The Bypass instruction allows users to test a device without passing
through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data
to be transferred through a device without affecting the operation of the device.
Pin Descriptions
Table 14: Pin Descriptions
Pin
Function
Description
TDI/RSI
Test Data In for JTAG /RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VCC if
unused.
TRSTB/RRO
Active low Reset for JTAG /RAM init.
reset out
Hold LOW during normal operation. Connects to serial PROM
reset for RAM initialization. Connect to GND if unused.
TMS
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to VCC if not
used for JTAG.
TCK
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to VCC
or ground if not used for JTAG.
TDO/RCO
Test data out for JTAG /RAM init.
clock out
Connect to serial PROM clock for RAM initialization. Must be
left unconnected if not used for JTAG or RAM initialization.
STM
Special Test Mode
Must be grounded during normal operation.
I/ACLK
High-drive input and/or array
network driver
Can be configured as either or both.
I/GCLK
High-drive input and/or global
network driver
Can be configured as either or both.
I
High-drive input
Use for input signals with high fanout.
I/O
Input/Output pin
Can be configured as an input and/or output.
V
CC
Power supply pin
Connect to 3.3 V supply.
VCCIO
Input voltage tolerance pin
Connect to 5.0 V supply if 5 V input tolerance is required,
otherwise connect to 3.3 V supply.
GND
Ground pin
Connect to ground.
GND/THERM
Ground/Thermal pin
Available on 456-PBGA only. Connect to ground plane on
PCB if heat sinking desired. Otherwise may be left
unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL4058-0PBN456M | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-0PQN208C | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| QL4058-0PQN208I | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| QL4058-0PQN208M | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| QL4058-1PBN456I | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
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