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參數(shù)資料
| 型號： | QL4058-0PQ208M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| 中文描述： | 58000可用門QuickRAM ESP PLD的結(jié)合性能，密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 271K |
| 代理商： | QL4058-0PQ208M |
14
www.quicklogic.com
2002 QuickLogic Corporation
QL4058 QuickRAM Data Sheet Rev H
The JTAG 1149.1 standard requires the following three tests:
Extest Instruction.
The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan
register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)
pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload
Instruction), and input boundary cells capture the input data for analysis.
Sample/Preload Instruction.
This instruction allows a device to remain in its
functional mode, while selecting the boundary scan register to be connected between
the TDI and TDO pins. For this test, the boundary scan register can be accessed via a
data scan operation, allowing users to sample the functional data entering and leaving
the device.
Bypass Instruction.
The Bypass instruction allows data to skip a device's boundary
scan entirely, so the data passes through the bypass register. The Bypass instruction
allows users to test a device without passing through other devices. The bypass register
connects the TDI and TDO pins, allowing serial data to be transferred through a device
without affecting the operation of the device.
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