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參數(shù)資料
| 型號(hào)： | QL4058-0PQ240M |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| 中文描述： | 58000可用門(mén)QuickRAM ESP PLD的結(jié)合性能，密度和嵌入式內(nèi)存 |
| 文件頁(yè)數(shù)： | 6/23頁(yè) |
| 文件大?。?/td> | 271K |
| 代理商： | QL4058-0PQ240M |
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6
www.quicklogic.com
2002 QuickLogic Corporation
QL4058 QuickRAM Data Sheet Rev H
Figure 4: QuickRAM Module
Table 2: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
5
t
SWA
WA Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWA
WA Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
SWD
WD Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWD
WD Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
SWE
WE Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
t
HWE
WE Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
t
WCRD
WCLK to RD (WA=RA)
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
5.0
5.3
5.6
5.9
7.1
Table 3: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
Logic Cells
1
2
3
4
5
t
SRA
RA Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
t
HRA
RA Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
t
SRE
RE Setup Time to RCLK
1.0
1.0
1.0
1.0
1.0
t
HRE
RE Hold Time to RCLK
0.0
0.0
0.0
0.0
0.0
t
RCRD
RCLK to RD
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the Operating Range.
4.0
4.3
4.6
4.9
6.1
WA
WD
WE
WCLK
RE
RCLK
RA
RD
[8:0]
[17:0]
[8:0]
[17:0]
MODE
ASYNCRD
[1:0]
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