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參數(shù)資料
| 型號(hào)： | QL4058-1PB456C |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 298K |
| 代理商： | QL4058-1PB456C |
6-53
QL4058 - QuickRAM
TM
RAM Cell Synchronous Read Timing
RAM Cell Asynchronous Read Timing
Input-Only/Clock Cells
Clock Cells
Notes:
[7]The array distributed networks consist of 40 half columns and the global distributed networks consist of 44
half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads
per half column.
Symbol
Parameter
Propagation Delays (ns)
Fanout
2
1.0
1.0
0.0
0.0
1.0
1.0
0.0
0.0
4.3
4.6
1
3
4
8
TSRA
THRA
TSRE
THRE
TRCRD
RA Setup Time to RCLK
RA Hold Time to RCLK
RE Setup Time to RCLK
RE Hold Time to RCLK
RCLK to RD [5]
1.0
0.0
1.0
0.0
4.0
1.0
0.0
1.0
0.0
4.9
1.0
0.0
1.0
0.0
6.1
Symbol
Parameter
Propagation Delays (ns)
Fanout
2
3.3
3.6
1
3
4
8
RPDRD
RA to RD [5]
3.0
3.9
5.1
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
3
1.6
1.8
1.9
1.7
1.9
2.0
3.1
3.1
3.1
0.0
0.0
0.0
0.8
1.0
1.1
0.7
0.9
1.0
2.3
2.3
2.3
0.0
0.0
0.0
1
4
8
12
2.9
3.0
3.1
0.0
2.1
2.0
2.3
0.0
24
4.4
4.5
3.1
0.0
3.6
3.5
2.3
0.0
TIN
TINI
TISU
TIH
TlCLK
TlRST
TlESU
TlEH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column
[7]
2
3
4
1.2
1.3
1.3
0.7
0.7
0.7
0.8
0.9
0.9
1
8
10
1.6
0.7
1.2
11
1.7
0.7
1.3
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1.2
0.7
0.8
1.5
0.7
1.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL4058-1PB456I | 58000 usable PLD gate quickRAM ESP combining performance，Density and Embedded RAM |
| QL4058-1PB456M | Field Programmable Gate Array (FPGA) |
| QL4058-1PQ208C | 58000 usable PLD gate quickRAM ESP combining performance，Density and Embedded RAM |
| QL4058-1PQ208I | Field Programmable Gate Array (FPGA) |
| QL4058-1PQ208M | 58000 usable PLD gate quickRAM ESP combining performance，Density and Embedded RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL4058-1PB456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-1PB456M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-1PQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-1PQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL4058-1PQ208M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
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