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| 型號： | QL4058-1PBN456M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-034BAR-2, BGA-456 |
| 文件頁數(shù)： | 41/45頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | QL4058-1PBN456M |
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2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
5
Electrical Specifications
AC Characteristics at V
CC = 3.3 V, TA = 25° C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 12 by the numbers provided in Table 3
through Table 10.
Table 3: Logic Cell
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
5
tPD
Combinatorial Delaya
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net
delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
1.4
1.7
1.9
2.2
3.2
tSU
Setup Time
a
1.7
tH
Hold Time
0.0
tCLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
tCWHI
Clock High Time
1.2
tCWLO
Clock Low Time
1.2
tSET
Set Delay
1.0
1.3
1.5
1.8
2.8
tRESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
tSW
Set Width
1.9
tRW
Reset Width
1.8
Table 4: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
5
tSWA
WA Setup Time to WCLK
1.0
tHWA
WA Hold Time to WCLK
0.0
tSWD
WD Setup Time to WCLK
1.0
tHWD
WD Hold Time to WCLK
0.0
t
SWE
WE Setup Time to WCLK
1.0
t
HWE
WE Hold Time to WCLK
0.0
t
WCRD
WCLK to RD (WA=RA)a
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
5.0
5.3
5.6
5.9
7.1
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