- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296940 > QL4058-1PQN208I (QUICKLOGIC CORP) FPGA, 1008 CLBS, 131328 GATES, PQFP208 PDF資料下載
參數(shù)資料
| 型號： | QL4058-1PQN208I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MO-136, QFP-208 |
| 文件頁數(shù)： | 3/45頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | QL4058-1PQN208I |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
11
JTAG
Figure 9: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the
least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response
to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan
Architecture.
The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of
a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with
the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests
for fuller verification of higher level system elements.
The 1149.1 standard requires the following three tests:
Extest Instruction. The Extest Instruction performs a Printed Circuit Board (PCB) interconnect test. This
test places a device into an external boundary test mode, selecting the boundary scan register to be
connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are
preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input
data for analysis.
Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this
test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the
functional data entering and leaving the device.
TCK
TMS
TRSTB
RDI
TDO
Instruction Decode
and
Control Logic
TAP Controller
State Machine
(16 States)
Instruction Register
Boundary-ScanRegister
(Data Register)
Mux
Bypass
Register
Mux
Internal
Register
I/O Registers
User Defined Data Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL4058-1PQN208M | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| QL4058-2PBN456C | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-2PBN456I | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-2PBN456M | FPGA, 1008 CLBS, 131328 GATES, PBGA456 |
| QL4058-2PQN208C | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL4058-2PB456C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA|1008-CELL|CMOS|BGA|456PIN|PLASTIC |
| QL4058-2PB456I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL4058-2PB456M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-2PQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL4058-2PQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。