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參數(shù)資料
| 型號： | QL4058-2PQ208I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | 58000 usable PLD gate quickRAM ESP combining performance，Density and Embedded RAM |
| 中文描述： | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MO-136, QFP-208 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 298K |
| 代理商： | QL4058-2PQ208I |
44
Preliminary
QL4058 - QuickRAM
TM
6-44
FIGURE 2. QuickRAM Module
Software support for the complete QuickRAM fam-
ily, including the QL4016, is available through two
basic packages. The turnkey QuickWorks
TM
pack-
age provides the most complete ESP software solu-
tion from design entry to logic synthesis, to place and
route, to simulation. The QuickTools
TM
for Worksat-
tions package provides a solution for designers who
use Cadence, Exemplar, Mentor, Syn-opsys, Synplic-
ity, Viewlogic, Veribest, or other third-party tools for
design entry, synthesis, or simulation.
The QuickLogic variable grain logic cell features up
to 16 simultaneous inputs and 5 outs within a cell
that can be fragmented into 5 independent cells.
Each cell has a fan-in of 29 including register and
control lines (see Figure 4).
FIGURE 3. QuickRAM Module bits
Product Summary
Product Summary
Total of 252 I/O Pins
I
244 bi-directional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
I
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
I
Two array clock/controlnetworks available to the logic
cell flip-flop clock, set and reset inputs - each driven by
and input-only pin
I
Six global clock/control networks available to the logic
cell F1, clock, set and reset inputs and the input and I/O
register clock, reset and enable inputs as well as the out-
put enable control - each driven by an input-only or I/O
pin, or any logic cell output or I/O cell feedback
High Performance
I
Input + logic cell + output total delays under 6 ns
I
Data path speeds over 400 MHz
I
Counter speeds over 300 MHz
I
FIFO speeds over 160+ MHz
FIGURE 4. Logic Cell
WDATA
RDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(1,152 bits)
RAM
Module
(1,152 bits)
P
RODUCT
S
UMMARY
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
QC
AZ
OZ
QZ
NZ
FZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL4058-2PQ208M | Field Programmable Gate Array (FPGA) |
| QL4058-2PQ240C | 58000 usable PLD gate quickRAM ESP combining performance，Density and Embedded RAM |
| QL4058-2PQ240I | Field Programmable Gate Array (FPGA) |
| QL4058-2PQ240M | 58000 usable PLD gate quickRAM ESP combining performance，Density and Embedded RAM |
| QL4058-3PB456C | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL4058-2PQ208M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-2PQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-2PQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-2PQ240M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
| QL4058-3PB456C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM |
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