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參數(shù)資料
| 型號(hào)： | QL5064-33BPB456I |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 10/37頁 |
| 文件大?。?/td> | 806K |
| 代理商： | QL5064-33BPB456I |
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QL5064 QuickPCI Data Sheet
10.0 DataOUT Bus Description
The DataOUT bus is used to transfer data from the back-end interface to the PCI bus. This bus is
connected to three destinations within the QL5064 device: one of the two DMA transmit FIFOs, or the
Target Read/Pre-Fetch FIFO. For proper data management and high data throughput, full and almost
full flags are available for each of the two DMA transmit FIFOs. The almost full flags are fully
configurable via the Control_DATA bus interface or the PCI bus. Interface to the Target Read/Pre-Fetch
FIFO is accomplished through the Target interface signals. A block diagram of the DataOUT
connections can be seen in Figure 7.
The data_outDES[1:0] signals select a particular FIFO to be connected to the DataOUT bus. A block
diagram of the DataOUT bus and its connections can be seen in Figure 7.
Data written to the DMA transmit FIFOs or the Target Read/Pre-fetch FIFO must be set up in the same
byte lanes in which the data will be transferred in the PCI bus. To aid with aligning, re-aligning, or
compacting data that is to be written to the FIFOs via the DataOUT bus, a byte-lane barrel shifter is
present, controlled by the data_out_shift[2:0] signals. See the DataOUT bus section of the internal signal
descriptions table for more information.
Figure 7: DataOUT and Control Bus Description
Fifo 0
Transmit
Control
Bus
Interface
data_out
Lane
Shifter
&
Construction
Fifo 1
Transmit
Target
Read
Fifo
To Master
Controller
To Target
Controller
0
1
0
1
0
1
0
1
0
1
0
1
WR
WR
WR
0
1
0
1
0
1
(cntl_addr == 0xc0 ) * ctrl_cs
(cntl_addr == 0xc8 ) * ctrl_cs
(cntl_addr == 0xf8) * ctrl_cs
cntl_data[63:0]
byte_lane [7:0]
data_out_h [63:0]
data_out_BEh[7:0]
cntl_data_out [63:0]
cntl_data_in [63:0]
data_out [63:0]
data_outDES[1:0]
data_outCS
user_clk
data_out_BE[7:0]
data_out_byte_sel[2:0]
fpga_reset
user_clk
FPGA
PCI Core
cntl_wrt_nrd
cntl_be[7:0]
cntl_addr [7:3]
cntl_cs
2
Detailed in Figure 3–17
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