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參數(shù)資料
| 型號(hào)： | QL8150 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 3/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8150 |
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Preliminary
6
!&
The Eclipse-II
logic cell structure is presented in
0
today's register-intensive designs.
. This architectural feature addresses
The Eclipse-II logic cell structure presented in
0
cell. It is designed for wide fan-in and multiple, simultaneous output funtions. Both registers share
CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its
input. The register can be loaded from the NZ output or directly from a dedicated input.
is a dual register, multiplexor-based logic
NOTE:
'&&&(&(&'&&'
&''')*+,-&&'.+/'
&&&&&&&'&&
The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven two-
to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell
has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17
simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic
capacity and fan-in of the logic cell accommodates many user functions with a single level of logic
delay while other architectures require two or more levels of delay.
01&,&
""
'"
&',
',
Multiplexer
16:1
5 ns
2.8 ns
Parity Tree
24
6 ns
3.4 ns
Counter
36
6 ns
3.4 ns
16 bit
250 MHz
450 MHz
32 bit
250 MHz
450 MHz
FIFO
128 x 32
155 MHz
280 MHz
256 x 16
155 MHz
280 MHz
128 x 64
155 MHz
280 MHz
Clock-to-Out
4.5 ns
2.5 ns
System clock
200 MHz
400 MHz
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