參數(shù)資料
型號(hào): QL8X12B-CF208M
廠商: Electronic Theatre Controls, Inc.
英文描述: Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
中文描述: 軍事5.0V帕希奇1家庭-非常高速的CMOS的FPGA
文件頁(yè)數(shù): 9/16頁(yè)
文件大?。?/td> 325K
代理商: QL8X12B-CF208M
8-15
Military 5.0V pASIC 1 Family
QL8X12B
AC CHARACTERISTICS at VCC = 5V, TA = 25
°
C (K = 1.00)
Logic Cell
Input Cells
Output Cell
Notes:
[6] See High Drive Buffer Table for more information.
[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half
columns used does not affect clock buffer delay.
[8] The following loads are used for tPXZ:
QL8
X
12B
Propagation Delays (ns)
Fanout
2
3
2.1
2.6
2.1
2.1
0.0
0.0
1.5
1.9
2.0
2.0
2.0
2.0
2.1
2.6
1.8
2.2
1.9
1.9
1.8
1.8
Symbol
Parameter
1
4
8
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [5]
Setup Time [5]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.7
2.1
0.0
1.0
2.0
2.0
1.7
1.5
1.9
1.8
3.0
2.1
0.0
2.3
2.0
2.0
3.0
2.5
1.9
1.8
4.8
2.1
0.0
4.2
2.0
2.0
4.8
3.9
1.9
1.8
Symbol
Parameter
Propagation Delays (ns)
[4]
1
2
3
4
6
8
tIN
tINI
tIO
tGCK
tGCKHI
tGCKLO
High Drive Input Delay [6]
High Drive Input, Inverting Delay [6]
Input Delay (bidirectional pad)
Clock Buffer Delay [7]
Clock Buffer Min High [7]
Clock Buffer Min Low [7]
2.1
2.1
1.4
2.7
2.0
2.0
2.2
2.2
1.8
2.7
2.0
2.0
2.3
2.3
2.2
2.8
2.0
2.0
2.4
2.5
2.6
2.9
2.0
2.0
2.6
2.8
3.4
3.0
2.0
2.0
2.9
3.1
4.2
Propagation Delays (ns)
[4]
Output Load Capacitance (pF)
50
75
3.4
4.2
3.7
4.7
4.9
6.1
4.2
5.0
Symbol
Parameter
30
2.7
2.8
4.0
3.6
2.9
3.3
100
5.0
5.6
7.3
5.8
150
6.7
7.6
9.7
7.3
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-state [8]
Output Delay Low to Tri-state [8]
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