參數(shù)資料
型號(hào)： QLUS3216-PT280C
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁(yè)數(shù)： 8/22頁(yè)
文件大?。?/td> 198K
代理商： QLUS3216-PT280C
8
www.quicklogic.com
2001 QuickLogic Corporation
QLUS3216-PQ208C Device Data Sheet
The configuration pins are not intended for change during operation. They are usually
board wired to configure the device for operation.
Table 7: East Utopia Slave Receive Interface
Pin
Mode
Description
erxclk
In
50MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
erxdata[15:0]
Out
Receive data bus.
erxprty (O)
Out
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
erxsoc
Out
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
erxenb
In
Active low transmit data transfer enable.
erxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
rxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
erxaddr(4:0)
In
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
taddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
Table 8: Device Configuration Pins
Pin
Mode
Description
prty_en
In
Enable parity checking on the Utopia interface.
If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and
the rx parity input should be tied to 0. Also the tx parity pins can be left open.
cellsize[7:0]
In
Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by
board wiring.
The size must be a multiple of 2 and cellsize[0] becomes a "not connected" and
should be left open.
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