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| 型號： | QLUS3316-PT280C |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 198K |
| 代理商： | QLUS3316-PT280C |
QLUS3216-PQ208C Device Data Sheet
7
QLUS3216-PQ208C Device Data Sheet
NOTE:
(O) indicates optional signals.
Table 5: West Utopia Slave Receive Interface
Pin
Mode
Description
wrxclk
In
90MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk
rising edge.
wrxdata[15:0]
Out
Receive data bus.
wrxprty (O)
Out
Receive data bus parity. Standard odd or non standard even parity can be
optionally generated by the Utopia Slave Core.
When the parity generation is disabled during the Core configuration, the pin
rxprty can be let unconnected.
wrxsoc
Out
Receive start of cell. Asserted to indicate that the current word is the first word of
a cell.
wrxenb
In
Active low transmit data transfer enable.
wrxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space one cell available in the FIFO.
wrxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected, one rxclav signal is implemented per PHY port. The
maximum number of clav signals is limited to four.
wrxaddr(4:0)
In
Utopia receive address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
Table 6: East Utopia Slave Transmit Interface
Pin
Mode
Description
etxclk
In
50MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk
rising edge.
etxdata[15:0]
In
Transmit data bus.
etxprty
In
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be left open.
etxsoc
In
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
etxenb
In
Active low transmit data transfer enable.
etxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
etxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited
to four.
etxaddr[4:0]
In
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
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