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參數(shù)資料
| 型號(hào)： | QLUS3332-PT280C |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 6/22頁(yè) |
| 文件大小： | 198K |
| 代理商： | QLUS3332-PT280C |
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2001 QuickLogic Corporation
QLUS3216-PQ208C Device Data Sheet
NOTE:
wtx_.. signals are sampled with west transmit clock (wtxclk). etx_.. signals are
sampled with west receive clock (wrxclk).
Table 4: West Utopia Slave Transmit Interface
NOTE:
(O) indicates optional signals.
Table 3: Device Management Interface
Pin
Mode
Description
wtx_err
Out
Transmit error indication on west interface. When driven high, indicates that an
errored cell (Wrong parity or wrong length) was received from the device
connected to the west interface and is discarded.
wtx_err_stat(1:0)
Out
Transmit error status information for west interface. When wtx_err is driven,
indicates the error status of the discarded cell:
wtx_err_stat(0) : When set to '1' indicates that a cell is discarded because of
a parity error.
wtx_err_stat(1) : When set to '1' indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
etx_err
Out
Transmit error indication on east interface. When driven high, indicates that an
errored cell (Wrong parity or wrong length) was received from the device
connected to the east interface side.
etx_err_stat(1:0)
Out
Transmit error status information for east receive interface. When etx_err is
driven, indicates the error status of the discarded cell:
ex_err_stat(0) : When set to '1' indicates that a cell is discarded because of
a parity error.
etx_err_stat(1) : When set to '1' indicates that a cell is discarded because it
has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia
interface within less than a complete cell time).
Pin
Mode
Description
wtxclk
In
90MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk
rising edge.
wtxdata[15:0]
In
Transmit data bus.
wtxprty
In
Transmit data bus parity. Standard odd or non-standard even parity can be
optionally checked by the connected Slave.
When the parity check is disabled during the Core configuration, or not used in
the design, the pin txprty should be tied to '0'.
wtxsoc
In
Transmit start of cell. Asserted by the Master to indicate that the current word is
the first word of a cell.
wtxenb
In
Active low transmit data transfer enable.
wtxclav[0]
Out
Cell buffer available. Asserted in octet level transfers to indicate to the Master that
the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the
Master that the PHY port FIFO has space to accept one cell.
wtxclav[3:1] (O)
Out
Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status
indication is selected during the Core configuration, one txclav signal is
implemented per PHY port. The maximum number of clav signals is limited
to four.
wtxaddr[4:0]
In
Utopia transmit address. When the Core operates in MPHY mode, address bus
used during polling and slave port selection. Bit 4 is the MSB.
txaddr(4:0) becomes optional (And should be left open) when the Core does not
operate in MPHY mode.
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