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參數(shù)資料
| 型號(hào)： | QS5820BTQ2 |
| 英文描述： | Five Distributed-Output Clock Driver |
| 中文描述： | 五分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 80K |
| 代理商： | QS5820BTQ2 |
1
COMMERCIAL TEMPERATURE RANGE
QS5820T
GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER
INA
OEA
5
OA
1
-OA
5
INB
OEB
5
OB
1
-OB
5
MONB
INC
OEC
5
OC
1
-OC
5
IND
OED
5
OD
1
-OD
5
MOND
DECEMBER 2000
2000 Integrated Device Technology, Inc.
DSC-5822/-
c
QS5820T
COMMERCIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS 20 OUTPUT
CLOCK DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
20 output, low skew clock signal buffer
High drive FCT-type outputs
Reduced swing TTL outputs for low noise
Input hysteresis for better noise margin
Monitor output
Guaranteed low skew
– 0.5ns output skew
– 0.7ns pulse skew
– 1ns part-to-part skew
Available in 40-pin QVSOP
DESCRIPTION:
The QS5820T clock driver/buffer circuits can be used for clock distri-
bution schemes where low skew, high speed, and small footprint are
primary concerns. The QS5820T offers four banks of five non-inverting
outputs. Designed in IDT's proprietary QCMOS process, this device
provides low propagation delay buffering with on-chip skew of 0.5ns for
same-transition, same-bank signals. The QS5820T provides major skew
advantages over octal type devices where total part-to-part skew (t
SK(t)
)
of >1ns is unacceptable. Furthermore, board area consumed by the
QVSOP package is almost one-third that of the typical SOIC package
offered for octal devices. This clock buffer product is designed for use in
high performance workstation, multi-board computing and telecommuni-
cations systems. The QS5820T is available in the 40-pin QVSOP pack-
age which offers the worlds smallest logic footprint.
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