參數(shù)資料
型號: QS5917T-100TJ
廠商: QUALITY SEMICONDUCTOR INC
元件分類: 時鐘及定時
英文描述: GIGATRUE 550 CAT6 YELLOW STRANDED BULK 500FT
中文描述: PLL BASED CLOCK DRIVER, PQCC28
文件頁數(shù): 3/7頁
文件大?。?/td> 62K
代理商: QS5917T-100TJ
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3
Pin Names
SYNC
0
SYNC
1
REF_SEL
FREQ_SEL
FEEDBACK
I/O
I
I
I
I
I
Description
Reference clock input
Reference clock input
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs.
Asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled (normal
operation).
PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes).
No Connection
Q
0
-Q
4
Q
5
2xQ
Q/2
LOCK
RST
O
O
O
O
O
I
PLL_EN
NC
I
PIN DESCRIPTION
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/
V
DD
= 5V ± 5%
Symbol
F
2XQ
F
Q
F
Q/2
Description
Max Frequency, 2xQ output
Max Frequency, Q
0
- Q
4
, Q
5
outputs
Max Frequency, Q/2
output
– 70
70
35
17.5
– 100
100
50
25
– 132
132
66
33
Units
MHz
MHz
MHz
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